US 9,812,408 B2
Semiconductor device with electrostatic discharge protection device near the edge of the chip
Shigeru Hirata, Kyoto (JP)
Assigned to Rohm Co., Ltd., Kyoto (JP)
Filed by Shigeru Hirata, Kyoto (JP)
Filed on Jul. 1, 2005, as Appl. No. 11/173,615.
Claims priority of application No. 2004-196864 (JP), filed on Jul. 2, 2004; and application No. 2005-185872 (JP), filed on Jun. 27, 2005.
Prior Publication US 2006/0001101 A1, Jan. 5, 2006
Int. Cl. H01L 23/62 (2006.01); H01L 23/58 (2006.01); H01L 27/02 (2006.01); H01L 23/00 (2006.01)
CPC H01L 23/585 (2013.01) [H01L 24/06 (2013.01); H01L 27/0251 (2013.01); H01L 27/0292 (2013.01); H01L 2224/05554 (2013.01); H01L 2924/12036 (2013.01); H01L 2924/1306 (2013.01); H01L 2924/13091 (2013.01); H01L 2924/14 (2013.01); H01L 2924/3011 (2013.01)] 6 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a positive-side supply pad to which a positive-side supply voltage is fed;
a negative-side supply pad to which a negative-side supply voltage is fed;
a positive-side supply conductor that is electrically connected to the positive-side supply pad;
a negative-side supply conductor that is electrically connected to the negative-side supply pad;
an input/output pad via which a signal can be fed in from outside the semiconductor device or fed to outside the semiconductor device;
a first electrostatic protection device that is electrically connected to the input/output pad;
a second electrostatic protection device that is electrically connected in parallel with the first electrostatic protection device; and
an internal circuit that is electrically connected via a signal conductor to the input/output pad,
wherein the first electrostatic protection device, the input/output pad, and the internal circuit are arranged in this order from an area adjacent an edge of the semiconductor device toward a center of the semiconductor device,
wherein the second electrostatic protection device, the input/output pad, and the internal circuit are arranged in this order from an area adjacent an edge of the semiconductor device toward a center of the semiconductor device,
wherein each of the positive-side supply conductor and the negative-side supply conductor has a center line describing an arc in an area at a corner of the semiconductor device,
wherein the first electrostatic protection device comprises:
a first diode of which a cathode receives the positive-side supply voltage, and of which an anode is electrically connected to the input/output pad; and
a second diode of which a cathode is electrically connected to the input/output pad, and of which an anode receives the negative-side supply voltage, and
wherein the second electrostatic protection device comprises:
a P-channel MOS transistor of which a gate and a source receive the positive-side supply voltage, and of which a drain is electrically connected to the input/output pad; and
an N-channel MOS transistor of which a drain is electrically connected to the input/output pad, and of which a gate and a source receive the negative-side supply voltage.