US 9,812,405 B2
Semiconductor package and manufacturing method of the same
Guan-Yu Chen, Hsinchu (TW); Yu-Wei Lin, New Taipei (TW); Tin-Hao Kuo, Hsinchu (TW); and Chen-Shien Chen, Hsinchu County (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD., Hsinchu (TW)
Filed on Jul. 29, 2016, as Appl. No. 15/223,371.
Application 15/223,371 is a division of application No. 14/517,026, filed on Oct. 17, 2014, granted, now 9,431,351.
Prior Publication US 2016/0336281 A1, Nov. 17, 2016
Int. Cl. H01L 23/00 (2006.01); H01L 23/498 (2006.01); H01L 21/66 (2006.01); H01L 21/48 (2006.01); H01L 25/065 (2006.01)
CPC H01L 23/562 (2013.01) [H01L 21/4853 (2013.01); H01L 21/4857 (2013.01); H01L 22/12 (2013.01); H01L 22/20 (2013.01); H01L 23/49822 (2013.01); H01L 23/49827 (2013.01); H01L 23/49838 (2013.01); H01L 23/49894 (2013.01); H01L 24/81 (2013.01); H01L 23/49811 (2013.01); H01L 24/13 (2013.01); H01L 24/16 (2013.01); H01L 24/17 (2013.01); H01L 25/0655 (2013.01); H01L 2224/131 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/16235 (2013.01); H01L 2224/17106 (2013.01); H01L 2224/814 (2013.01); H01L 2224/81191 (2013.01); H01L 2224/81424 (2013.01); H01L 2224/81444 (2013.01); H01L 2224/81447 (2013.01); H01L 2224/81455 (2013.01); H01L 2224/81815 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/3511 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor package, comprising:
a substrate with a first warpage, the substrate comprising:
a middle layer;
a top metal overlying the middle layer, the top metal comprising:
a top metal trace horizontally patterned at a same height level; and
a top metal vias vertically connecting to the top metal trace; and
a bottom metal underlying the middle layer, the bottom metal comprising:
a bottom metal trace horizontally patterned at a same level; and
a bottom metal vias vertically connecting to the bottom metal trace,
wherein a bottom metal density is greater than a top metal density so as to achieve the first warpage, the bottom metal density being an areal ratio between the bottom metal trace and a size of the semiconductor package from a top view perspective, the top metal density being an areal ratio between the top metal trace and the size of the semiconductor package from a top view perspective; and
a device die over the substrate, having a second warpage and a surface area greater than about 100 mm2,
wherein the top metal trace of the substrate is directly connected to a metal bump of the device die through a solder, and
wherein warpage sign convention and warpage value for the first and second warpage are substantially identical before and after directly connecting the substrate and the device die.