US 9,812,403 B2
Reducing wafer warpage during wafer processing
Kenji Konomi, Nagoya (JP)
Assigned to TOSHIBA MEMORY CORPORATION, Minato-ku (JP)
Filed by TOSHIBA MEMORY CORPORATION, Minato-ku (JP)
Filed on Aug. 24, 2015, as Appl. No. 14/833,420.
Claims priority of provisional application 61/132,327, filed on Mar. 12, 2015.
Prior Publication US 2016/0268217 A1, Sep. 15, 2016
Int. Cl. H01L 21/67 (2006.01); H01L 23/00 (2006.01); H01L 23/58 (2006.01); H01L 21/784 (2006.01)
CPC H01L 23/562 (2013.01) [H01L 21/784 (2013.01); H01L 23/585 (2013.01); H01L 2924/14 (2013.01); H01L 2924/3511 (2013.01); H01L 2924/37001 (2013.01)] 6 Claims
OG exemplary drawing
 
2. A semiconductor wafer comprising:
a first guard ring surrounding a first chip region at a planar view;
a second guard ring surrounding a second chip region at a planar view; and
a joist structure mechanically connecting the first guard ring with the second guard ring,
wherein the joist structure includes a number of connection patterns connecting a first portion with a second portion, the first portion being a portion extending along the second guard ring in the first guard ring, the second portion being a portion extending along the first guard ring in the second guard ring, and
wherein a number of the connection patterns include
a first connection pattern connecting one end side of the first portion with one end side of the second portion,
a second connection pattern connecting another end side of the first portion with another end side of the second portion, and
a third connection pattern connecting the first portion with the second portion between the first connection pattern and the second connection pattern.