forming a liner layer within a first trench over an exposed first source/drain epitaxial region of a fin-shaped field-effect-transistor (FINFET) to substantially line the first trench, and forming the liner layer within a second trench over an exposed second source/drain epitaxial region of the FINFET to substantially line the second trench;

forming a sacrificial material over the liner layer within the first trench and the second trench to substantially fill the first trench and the second trench;

removing a portion of the sacrificial material and a portion of the liner layer from the first trench to expose a first portion of the first source/drain epitaxial region thereunder and from the second trench to expose a second portion of the second source/drain epitaxial region thereunder;

forming a dielectric film over the exposed first portion of the first source/drain epitaxial region within the first trench to form a first contact line spacer, and forming the dielectric film over the exposed second portion of the second source/drain epitaxial region within the second trench to form a second contact line spacer; and

planarizing to a top surface of the dielectric layer.