| US 9,812,399 B2 | ||
| Prevention of premature breakdown of interline porous dielectrics in an integrated circuit | ||
| Christian Rivero, Rousset (FR); Pascal Fornara, Pourrieres (FR); and Jean-Philippe Escales, Fuveau (FR) | ||
| Assigned to STMicroelectronics (Rousset) SAS, Rousset (FR) | ||
| Filed by STMicroelectronics (Rousset) SAS, Rousset (FR) | ||
| Filed on Apr. 25, 2016, as Appl. No. 15/137,063. | ||
| Claims priority of application No. 15 59337 (FR), filed on Oct. 1, 2015. | ||
| Prior Publication US 2017/0098615 A1, Apr. 6, 2017 | ||
| Int. Cl. H01L 23/48 (2006.01); H01L 23/532 (2006.01); H01L 21/768 (2006.01); H01L 21/02 (2006.01); H01L 23/528 (2006.01); H01L 23/522 (2006.01) | ||
| CPC H01L 23/53295 (2013.01) [H01L 21/02167 (2013.01); H01L 21/76829 (2013.01); H01L 21/76877 (2013.01); H01L 23/528 (2013.01); H01L 23/5226 (2013.01); H01L 23/53228 (2013.01); H01L 21/0217 (2013.01)] | 14 Claims |
| 1. An integrated circuit, comprising:
a semiconductor substrate having a top surface;
a porous portion of at least one dielectric region over said semiconductor substrate;
two electrically conductive lines of an interconnect portion; and
at least one non-porous dielectric barrier inserted between the porous portion of the at least one dielectric region and each
of said two electrically conductive elements of the interconnect portion, wherein the at least one non-porous dielectric barrier
does not extend along any lower surface of said two electrically conductive elements which extends parallel to the top surface
of the semiconductor substrate;
said non-porous dielectric barrier configured to protect said integrated circuit from breakdown of said at least one dielectric
region caused by electrical conduction assisted by the presence of defects located in said at least one dielectric region.
|