US 9,812,398 B2
Semiconductor memory device having memory cells provided in a height direction
Ming Hu, Yokkaichi (JP); Toshiyuki Takewaki, Yokkaichi (JP); and Seiichi Omoto, Yokkaichi (JP)
Assigned to TOSHIBA MEMORY CORPORATION, Minato-ku (JP)
Filed by Toshiba Memory Corporation, Minato-ku (JP)
Filed on Sep. 9, 2015, as Appl. No. 14/849,061.
Claims priority of provisional application 62/132,822, filed on Mar. 13, 2015.
Prior Publication US 2016/0268191 A1, Sep. 15, 2016
Int. Cl. H01L 29/10 (2006.01); H01L 31/036 (2006.01); H01L 31/112 (2006.01); H01L 23/532 (2006.01); H01L 27/11582 (2017.01); H01L 27/1157 (2017.01)
CPC H01L 23/53271 (2013.01) [H01L 27/1157 (2013.01); H01L 27/11582 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor memory device, comprising:
a memory string comprising a plurality of memory cells connected in series therein;
a first wiring electrically connected to one end of the memory string; and
a contact electrically connected between the memory string and the first wiring,
the memory string comprising:
a plurality of control gate electrodes as first conductive layers stacked above a substrate; and
a semiconductor layer having one end electrically connected to the contact and having as its longer direction a direction perpendicular to the substrate, the semiconductor layer facing the plurality of control gate electrodes, and
the contact comprising a contact layer, the contact layer having a plate-like shape whose longer direction is a first direction parallel to the substrate, and the contact layer having its lower surface electrically connected to the one end of the semiconductor layer, and
the contact layer comprising:
a metal layer that includes tungsten;
a silicon based layer that includes a material including silicon; and
a second conductive layer that covers side surfaces of the metal layer and the silicon based layer.