| US 9,812,396 B1 | ||
| Interconnect structure for semiconductor devices with multiple power rails and redundancy | ||
| Jason Eugene Stephens, Menands, NY (US); Guillaume Bouche, Albany, NY (US); Shreesh Narasimha, Beacon, NY (US); Patrick Ryan Justison, Clifton Park, NY (US); Byoung Youp Kim, Schenectady, NY (US); and Craig Michael Child, Jr., Gansevoort, NY (US) | ||
| Assigned to GLOBALFOUNDRIES INC., Grand Cayman (KY) | ||
| Filed by GLOBALFOUNDRIES Inc., Grand Cayman (KY) | ||
| Filed on Jun. 7, 2016, as Appl. No. 15/175,495. | ||
| Int. Cl. H01L 21/768 (2006.01); H01L 23/528 (2006.01); H01L 23/522 (2006.01); H01L 21/311 (2006.01) | ||
| CPC H01L 23/5286 (2013.01) [H01L 21/31144 (2013.01); H01L 21/7684 (2013.01); H01L 21/76802 (2013.01); H01L 21/76807 (2013.01); H01L 21/76883 (2013.01); H01L 23/5226 (2013.01); H01L 23/5283 (2013.01)] | 8 Claims |
| 1. A method, comprising:
providing a starting interconnect structure for one or more semiconductor devices, the starting interconnect structure comprising
a first metallization layer with a first power rail;
forming a second metallization layer over the first metallization layer with a second power rail;
directly electrically connecting the first power rail and the second power rail;
wherein the directly electrically connecting comprises forming a plurality of metal-filled vias between the first power rail
and the second power rail;
forming at least one additional metallization layer over the second metallization layer with at least one additional power
rail; and
directly electrically connecting each of the at least one additional power rail to a power rail of a metallization layer directly
below.
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