US 9,812,392 B2
Inductor system and method
Hsien-Wei Chen, Hsinchu (TW); Hung-Yi Kuo, Taipei (TW); Hao-Yi Tsai, Hsinchu (TW); and Tsung-Yuan Yu, Taipei (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on May 8, 2017, as Appl. No. 15/589,821.
Application 15/225,344 is a division of application No. 14/182,116, filed on Feb. 17, 2014, granted, now 9,406,739, issued on Aug. 2, 2016.
Application 15/589,821 is a continuation of application No. 15/225,344, filed on Aug. 1, 2016, granted, now 9,647,054.
Claims priority of provisional application 61/783,416, filed on Mar. 14, 2013.
Prior Publication US 2017/0243820 A1, Aug. 24, 2017
Int. Cl. H01L 23/522 (2006.01); H01L 21/768 (2006.01); H01L 49/02 (2006.01); H01L 23/58 (2006.01); H01L 21/311 (2006.01)
CPC H01L 23/5227 (2013.01) [H01L 21/31144 (2013.01); H01L 21/76802 (2013.01); H01L 21/76877 (2013.01); H01L 23/585 (2013.01); H01L 28/10 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of manufacturing a semiconductor device, the method comprising:
forming a first conductive element and a second conductive element within a first metallization layer over a semiconductor substrate;
forming a first via and a second via in electrical connection with the first conductive element, wherein no vias are formed in contact with the second conductive element;
forming a first coil over and in connection with the first via;
forming a second coil over and in connection with the second via, wherein the second coil is over but not in connection with the second conductive element; and
forming a third coil over but not in connection with the second conductive element, the third coil being electrically isolated from the second coil.