US 9,812,388 B2
Semiconductor device and manufacturing method thereof
Yoshihiko Shimanuki, Gunma (JP)
Assigned to Renesas Electronics Corporation, Tokyo (JP)
Filed by Renesas Electronics Corporation, Koutou-ku, Tokyo (JP)
Filed on Nov. 22, 2016, as Appl. No. 15/359,611.
Claims priority of application No. 2016-013151 (JP), filed on Jan. 27, 2016.
Prior Publication US 2017/0213788 A1, Jul. 27, 2017
Int. Cl. H01L 23/28 (2006.01); H01L 23/498 (2006.01); H01L 21/56 (2006.01); H01L 23/00 (2006.01); H01L 23/495 (2006.01)
CPC H01L 23/49861 (2013.01) [H01L 21/561 (2013.01); H01L 21/565 (2013.01); H01L 23/49513 (2013.01); H01L 23/49548 (2013.01); H01L 23/49555 (2013.01); H01L 23/49582 (2013.01); H01L 23/49838 (2013.01); H01L 24/45 (2013.01); H01L 24/48 (2013.01); H01L 24/49 (2013.01); H01L 2224/45147 (2013.01); H01L 2224/48101 (2013.01); H01L 2224/48245 (2013.01); H01L 2224/48458 (2013.01); H01L 2224/48465 (2013.01); H01L 2224/49171 (2013.01); H01L 2924/1711 (2013.01); H01L 2924/1811 (2013.01); H01L 2924/1815 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a chip mounting portion that includes a first upper surface and a first lower surface located on the opposite side of the first upper surface;
a semiconductor chip that includes a second upper surface, an electrode formed over the second upper surface, and a second lower surface located on the opposite side of the second upper surface and mounted over the first upper surface;
a lead;
a wire that connects the electrode of the semiconductor chip and the lead; and
a sealing body that includes a third upper surface and a third lower surface located on the opposite side of the third upper surface and seals the semiconductor chip, the wire, a part of the lead, and a part of the chip mounting portion,
wherein the first lower surface of the chip mounting portion is exposed from the third lower surface of the sealing body,
wherein the chip mounting portion and the wire are comprised of copper, and
wherein a thickness of the semiconductor chip is larger than the sum of a thickness of the chip mounting portion and a thickness from the second upper surface of the semiconductor chip to the third upper surface of the sealing body.