US 9,812,386 B1
Encapsulated semiconductor package
Ronald Patrick Huemoeller, Gilbert, AZ (US); Sukianto Rusli, Phoenix, AZ (US); and David Jon Hiner, Chandler, AZ (US)
Assigned to AMKOR TECHNOLOGY, INC., Tempe, AZ (US)
Filed by Amkor Technology, Inc., Tempe, AZ (US)
Filed on Dec. 23, 2014, as Appl. No. 14/581,556.
Application 12/387,691 is a division of application No. 11/497,617, filed on Aug. 1, 2006, granted, now 7,548,430.
Application 14/581,556 is a continuation of application No. 13/679,627, filed on Nov. 16, 2012, granted, now 9,691,635.
Application 13/679,627 is a continuation of application No. 12/387,691, filed on May 5, 2009, granted, now 8,341,835.
Int. Cl. H05K 7/00 (2006.01); H01L 23/498 (2006.01); H01L 23/31 (2006.01); H01L 23/552 (2006.01); H01L 23/00 (2006.01)
CPC H01L 23/49816 (2013.01) [H01L 23/31 (2013.01); H01L 23/552 (2013.01); H01L 24/14 (2013.01); H01L 24/30 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit package, comprising:
a laminate comprising:
a first laminate surface;
a second laminate surface opposite the first laminate surface; and
a plurality of side laminate surfaces connecting the first laminate surface and the second laminate surface;
an integrated circuit die comprising:
a first die surface;
a second die surface opposite the first die surface and coupled to the first laminate surface;
a plurality of side die surfaces connecting the first die surface and the second die surface; and
a bond pad on the first die surface;
an encapsulant that surrounds and contacts at least the first die surface and the plurality of side die surfaces, wherein the encapsulant is a single continuous encapsulating material that comprises:
a first encapsulant surface;
a second encapsulant surface opposite the first encapsulant surface and coupled to the first laminate surface; and
a plurality of side encapsulant surfaces connecting the first encapsulant surface and the second encapsulant surface,
wherein each of the plurality of side encapsulant surfaces is coplanar with a respective one of the plurality of side laminate surfaces;
a metal column comprising:
a first column end exposed from the first encapsulant surface;
a second column end coupled to the bond pad; and
a middle column portion that extends through the encapsulant between the first column end and the second column end; and
a redistribution structure formed on the first encapsulant surface, the redistribution structure comprising:
a plurality of build-up dielectric layers;
a ball pad outside a footprint of the integrated circuit die; and
a trace within the plurality of build-up dielectric layers, where the trace extends between the metal column within the footprint of the integrated circuit die and the ball pad and electrically couples the ball pad to the first column end.