US 9,812,384 B2
Semiconductor device having compliant and crack-arresting interconnect structure
Gregory Thomas Ostrowicki, Rockwall, TX (US)
Assigned to TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed by TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed on Nov. 15, 2016, as Appl. No. 15/352,393.
Application 15/352,393 is a continuation of application No. 15/053,453, filed on Feb. 25, 2016, granted, now 9,496,208.
Prior Publication US 2017/0250126 A1, Aug. 31, 2017
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 23/495 (2006.01); H01L 23/00 (2006.01); H01L 25/07 (2006.01)
CPC H01L 23/49575 (2013.01) [H01L 23/49562 (2013.01); H01L 24/32 (2013.01); H01L 24/40 (2013.01); H01L 24/73 (2013.01); H01L 25/074 (2013.01); H01L 2224/32245 (2013.01); H01L 2224/40245 (2013.01); H01L 2224/73213 (2013.01); H01L 2224/73263 (2013.01)] 22 Claims
OG exemplary drawing
 
1. A power converter comprising:
a first transistor chip that is coupled to and stacked on top of a second transistor chip; the second transistor chip having a first surface that is coupled to a leadframe pad; and
a first metallic clip having a plate portion and a ridge portion that is bent at an angle from the plate portion to a lead; the plate portion coupled to a first surface of the first transistor chip that is opposite to the second transistor chip; the ridge portion configured as a plurality of parallel straight fingers with each finger discretely attached to the lead and operable as a spring-line cantilever.