US 9,812,382 B2
Semiconductor device with lead terminals having portions thereof extending obliquely
Kazutaka Shibata, Kyoto (JP)
Assigned to ROHM CO., LTD., Kyoto (JP)
Filed by ROHM CO., LTD., Kyoto (JP)
Filed on Sep. 22, 2016, as Appl. No. 15/272,557.
Application 10/795,247 is a division of application No. 09/970,056, filed on Oct. 4, 2001, granted, now 6,710,431, issued on Mar. 23, 2004.
Application 15/272,557 is a continuation of application No. 14/716,238, filed on May 19, 2015, granted, now 9,472,492.
Application 14/716,238 is a continuation of application No. 14/132,019, filed on Dec. 18, 2013, granted, now 9,064,855, issued on Jun. 23, 2015.
Application 14/132,019 is a continuation of application No. 13/832,377, filed on Mar. 15, 2013, granted, now 8,637,976, issued on Jan. 28, 2014.
Application 13/832,377 is a continuation of application No. 13/223,364, filed on Sep. 1, 2011, granted, now 8,421,209, issued on Apr. 16, 2013.
Application 13/223,364 is a continuation of application No. 12/659,733, filed on Mar. 19, 2010, granted, now 8,026,591, issued on Sep. 27, 2011.
Application 12/659,733 is a continuation of application No. 10/795,247, filed on Mar. 9, 2004, granted, now 7,705,444, issued on Apr. 27, 2010.
Claims priority of application No. 2000-307377 (JP), filed on Oct. 6, 2000.
Prior Publication US 2017/0011990 A1, Jan. 12, 2017
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 23/495 (2006.01); H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 23/31 (2006.01); H01L 23/00 (2006.01)
CPC H01L 23/49548 (2013.01) [H01L 21/4825 (2013.01); H01L 21/4842 (2013.01); H01L 21/565 (2013.01); H01L 23/3107 (2013.01); H01L 23/3114 (2013.01); H01L 23/495 (2013.01); H01L 23/4952 (2013.01); H01L 23/49503 (2013.01); H01L 23/49541 (2013.01); H01L 24/49 (2013.01); H01L 24/48 (2013.01); H01L 2224/05599 (2013.01); H01L 2224/451 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48106 (2013.01); H01L 2224/48247 (2013.01); H01L 2224/85399 (2013.01); H01L 2924/00014 (2013.01); H01L 2924/181 (2013.01)] 9 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a semiconductor chip having a plurality of electrodes on a first surface thereof;
a first lead having a supporting portion for mounting a semiconductor chip thereon and a projecting portion which projects in a first direction from the supporting portion;
a second lead extending in a second direction non-parallel with the first direction;
one or more third leads extending in the second direction, such that a line extending in a third direction perpendicular to the first direction passes through the second lead and the one or more third leads;
a plurality of wires connecting the plurality of electrodes with the second lead and the one or more third leads; and
a resin covering the semiconductor chip, the first lead, the second lead, the plurality of third leads, and the plurality of wires,
wherein the second lead has a first surface and a side surface, such that one of the plurality of wires is connected to the second lead on the first surface,
wherein the second lead includes a first portion and a second portion, the first portion having a width larger than the second portion, the first portion having one side parallel to the first direction, and the first portion located between the second portion and the first lead,
wherein the side surface of the second lead is exposed from the resin and is co-planar with an outer surface of the resin,
wherein the one or more third leads each includes a first portion, a second portion, and a third portion, such that the first portion is located between the second portion and the third portion and has a width greater than the second portion and the third portion, and
wherein the one or more third leads each includes a first surface and a side surface, such that one of the plurality of wires is connected to the one or more third leads on the first surface,
wherein the side surface of the third lead is exposed from the resin and is co-planar with an outer surface of the resin.