US 9,812,379 B1
Semiconductor package and manufacturing method
Jui-Chieh Chiu, Taoyuan (TW); Chih-Wen Huang, Taoyuan (TW); and You-Cheng Lai, Taoyuan (TW)
Assigned to WIN Semiconductors Corp., Tao Yuan (TW)
Filed by WIN Semiconductors Corp., Tao Yuan (TW)
Filed on Oct. 19, 2016, as Appl. No. 15/298,221.
Int. Cl. H01L 21/00 (2006.01); H01L 23/02 (2006.01); H01L 23/495 (2006.01); H01L 23/498 (2006.01); H01L 21/48 (2006.01)
CPC H01L 23/4951 (2013.01) [H01L 21/4853 (2013.01); H01L 23/49811 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A manufacturing method of a plurality of semiconductor packages, wherein the manufacturing method is performed before an assembly process for the plurality of semiconductor packages, the method comprising:
forming signal leads and ground leads directly under a back side of a wafer, wherein the wafer comprises a plurality of dies, each die comprises at least a via and a least a hot via, and the at least a via and the at least a hot via penetrate through the die;
forming at least a metal sheet on a top side of the die, wherein the at least a metal sheet is directly connected to the at least a via or the at least a hot via;
forming a buffer layer on the top of wafer to cover the metal sheet;
forming a molding portion on the buffer layer, wherein the buffer layer isolates the at least a metal sheet from being contacted by the molding portion, and the molding portion has no contact with the ground lead or the signal lead; and
dividing the wafer, the buffer layer and the molding portion into the plurality of semiconductor packages.