US 9,812,378 B2
Packaging for high power integrated circuits and infrared emitter arrays
Jim Oleson, Santa Barbara, CA (US); and Roger Holcombe, Santa Barbara, CA (US)
Assigned to OLESON CONVERGENT SOLUTIONS LLC, Santa Barbara, CA (US)
Filed by Oleson Convergent Solutions, LLC, Santa Barbara, CA (US)
Filed on May 8, 2017, as Appl. No. 15/589,431.
Application 15/589,431 is a division of application No. 14/327,307, filed on Jul. 9, 2014, granted, now 9,706,655.
Claims priority of provisional application 61/844,246, filed on Jul. 9, 2013.
Prior Publication US 2017/0243807 A1, Aug. 24, 2017
Int. Cl. H01L 21/00 (2006.01); H01L 23/473 (2006.01); H01L 21/48 (2006.01); H01L 23/04 (2006.01); H01L 23/40 (2006.01); H01L 23/538 (2006.01); H01L 25/065 (2006.01); H05B 33/06 (2006.01); H05B 33/10 (2006.01)
CPC H01L 23/473 (2013.01) [H01L 21/4817 (2013.01); H01L 21/4878 (2013.01); H01L 21/4882 (2013.01); H01L 23/04 (2013.01); H01L 23/4006 (2013.01); H01L 23/5384 (2013.01); H01L 23/5389 (2013.01); H01L 25/0655 (2013.01); H05B 33/06 (2013.01); H05B 33/10 (2013.01); H01L 2023/4018 (2013.01); H01L 2023/4087 (2013.01)] 27 Claims
OG exemplary drawing
 
1. A method of fabricating a package for controlling temperature and avoiding thermally induced stress in a high power silicon component, the method comprising the steps of:
fabricating a body of the package from a material having a Coefficient of Thermal Expansion (CTE) compatible with the CTE of the silicon component, the body having a plurality of sides and defining a top surface, a bottom surface, and an internal cavity;
rigidly affixing a conductive material within the internal cavity; and
installing a plurality of feedthrus to the body of the package, a first feedthru extending from one of the plurality of sides and a second feedthru extending from another of the plurality of sides, each feedthru defining a passageway into the internal cavity, thereby allowing coolant to flow from an outside source through the internal cavity of the body, wherein the high power silicon component is taken from a list comprising high power silicon integrated circuits and high power silicon emitter arrays,
wherein the package is configured to facilitate rigidly affixing the high power silicon component to the body of the package at a first temperature,
wherein the package is configured to facilitate operating the high power silicon component at least at a second temperature, and
wherein at least one of the first and second temperatures is room temperature and wherein the other of the first and second temperatures is a cryogenic temperature.