US 9,812,370 B2
III-V, SiGe, or Ge base lateral bipolar transistor and CMOS hybrid technology
Josephine B. Chang, Ellicott City, MD (US); Gen P. Lauer, Yorktown Heights, NY (US); Isaac Lauer, Yorktown Heights, NY (US); and Jeffrey W. Sleight, Ridgefield, CT (US)
Assigned to International Business Machines Corporation, Armonk, NY (US)
Filed by International Business Machines Corporation, Armonk, NY (US)
Filed on Oct. 24, 2016, as Appl. No. 15/332,207.
Application 15/332,207 is a division of application No. 14/245,627, filed on Apr. 4, 2014, granted, now 9,496,184.
Prior Publication US 2017/0040219 A1, Feb. 9, 2017
Int. Cl. H01L 21/336 (2006.01); H01L 21/8249 (2006.01); H01L 29/66 (2006.01); H01L 21/24 (2006.01); H01L 29/10 (2006.01); H01L 29/45 (2006.01); H01L 29/735 (2006.01); H01L 27/06 (2006.01); H01L 21/84 (2006.01)
CPC H01L 21/8249 (2013.01) [H01L 21/244 (2013.01); H01L 21/84 (2013.01); H01L 27/0623 (2013.01); H01L 29/1008 (2013.01); H01L 29/456 (2013.01); H01L 29/6625 (2013.01); H01L 29/66545 (2013.01); H01L 29/735 (2013.01)] 10 Claims
OG exemplary drawing
 
1. A method of co-fabricating at least one CMOS FET device and at least one bipolar transistor device on a wafer, the method comprising the steps of:
forming at least one CMOS FET dummy gate and at least one bipolar transistor dummy gate on the wafer, wherein the CMOS FET dummy gate is present over a portion of the wafer that serves as a channel region of the CMOS FET device and the bipolar transistor dummy gate is present over a portion of the wafer that serves as a base of the bipolar transistor;
doping the wafer to form emitter and collector regions on both sides of the bipolar transistor dummy gate;
doping the wafer to form source and drain regions on both sides of the CMOS FET dummy gate;
depositing a dielectric filler layer onto the wafer surrounding the CMOS FET dummy gate and the bipolar transistor dummy gate;
removing the CMOS FET dummy gate and the bipolar transistor dummy gate selective to the dielectric filler layer, wherein removal of the CMOS FET dummy gate results in at least one first trench being formed in the dielectric filler layer and removal of the bipolar transistor dummy gate results in at least one second trench being formed in the dielectric filler layer;
recessing the base of the bipolar transistor;
re-growing the base of the bipolar transistor from an epitaxial material selected from the group consisting of: SiGe, Ge, and a III-V material;
forming a replacement gate of the CMOS FET device in the first trench over the channel region of the CMOS FET device; and
forming contacts to the replacement gate of the CMOS FET device and to the base of the bipolar transistor device.