US 9,812,369 B2
BiMOS device with a fully self-aligned emitter-silicon and method for manufacturing the same
Frank Hoffmann, Freiberg (DE); Dirk Manger, Dresden (DE); Andreas Pribil, Dresden (DE); Marc Probst, Radeberg (DE); and Stefan Tegen, Dresden (DE)
Assigned to Infineon Technologies AG, Neubiberg (DE)
Filed by Infineon Technologies AG, Neubiberg (DE)
Filed on Mar. 29, 2016, as Appl. No. 15/83,774.
Claims priority of application No. 10 2015 208 133 (DE), filed on Apr. 30, 2015.
Prior Publication US 2016/0322257 A1, Nov. 3, 2016
Int. Cl. H01L 21/8249 (2006.01); H01L 27/06 (2006.01); H01L 29/06 (2006.01); H01L 29/08 (2006.01); H01L 29/10 (2006.01); H01L 29/66 (2006.01); H01L 29/737 (2006.01)
CPC H01L 21/8249 (2013.01) [H01L 27/0623 (2013.01); H01L 29/0649 (2013.01); H01L 29/0692 (2013.01); H01L 29/0804 (2013.01); H01L 29/0817 (2013.01); H01L 29/0821 (2013.01); H01L 29/1004 (2013.01); H01L 29/66242 (2013.01); H01L 29/66272 (2013.01); H01L 29/7371 (2013.01)] 25 Claims
OG exemplary drawing
 
1. A method for manufacturing a bipolar junction transistor, the method comprising:
providing a substrate of a first conductive type and a layer stack arranged on the substrate, wherein the layer stack comprises a first isolation layer arranged on a surface region of the substrate, a sacrificial layer arranged on the first isolation layer and a second isolation layer arranged on the sacrificial layer, wherein the layer stack comprises a window formed in the layer stack through the second isolation layer, the sacrificial layer, and the first isolation layer up to the surface region of the substrate;
providing a collector layer of a first semi conductive type on the substrate within the window of the layer stack;
providing a base layer of a second semi conductive type on the collector layer within the window of the layer stack;
providing an emitter layer or an emitter layer stack comprising the emitter layer on the base layer within the window of the layer stack, such that an overfill of the window of the layer stack is achieved, wherein the emitter layer is of the first semi conductive type; and
selectively removing the emitter layer or the emitter layer stack at least up to the second isolation layer.