US 9,812,367 B2
Method for fabricating semiconductor device including replacement process of forming at least one metal gate structure
Ju-Youn Kim, Suwon-si (KR); Ji-Hwan An, Seoul (KR); Kwang-Yul Lee, Suwon-si (KR); Tae-Won Ha, Seongnam-si (KR); and Jeong-Nam Han, Seoul (KR)
Assigned to Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do (KR)
Filed by Ju-Youn Kim, Suwon-si (KR); Ji-Hwan An, Seoul (KR); Kwang-Yul Lee, Suwon-si (KR); Tae-Won Ha, Seongnam-si (KR); and Jeong-Nam Han, Seoul (KR)
Filed on Feb. 13, 2015, as Appl. No. 14/621,440.
Claims priority of application No. 10-2014-0070148 (KR), filed on Jun. 10, 2014.
Prior Publication US 2015/0357426 A1, Dec. 10, 2015
Int. Cl. H01L 21/8234 (2006.01); H01L 29/66 (2006.01); H01L 29/51 (2006.01); H01L 21/28 (2006.01); H01L 29/49 (2006.01); H01L 21/311 (2006.01); H01L 21/3213 (2006.01)
CPC H01L 21/82345 (2013.01) [H01L 21/28185 (2013.01); H01L 21/823431 (2013.01); H01L 29/513 (2013.01); H01L 29/517 (2013.01); H01L 29/66545 (2013.01); H01L 29/66795 (2013.01); H01L 21/28088 (2013.01); H01L 21/31138 (2013.01); H01L 21/32139 (2013.01); H01L 29/4966 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A method of fabricating a semiconductor device, the method comprising:
forming an inter-metal dielectric layer having a first trench and a second trench which are spaced from each other, on a substrate, whereby each of the trenches has sides and a bottom;
forming a first dielectric layer along the sides and bottom of the first trench;
forming a second dielectric layer along the sides and bottom of the second trench;
forming a first lower conductive layer and a second lower conductive layer respectively on the first dielectric layer and the second dielectric layer;
forming a first capping layer and a second capping layer respectively on the first lower conductive layer and the second lower conductive layer;
performing a heat treatment after the first and second capping layers have been formed;
removing the first and second capping layers and the first and second lower conductive layers after performing the heat treatment; and
forming first and second metal gate structures respectively on the first and second dielectric layers,
wherein the forming of the first and second lower conductive layers comprises forming a TiN layer on the first and second dielectric layers.