US 9,812,365 B1
Methods of cutting gate structures on transistor devices
John H. Zhang, Altamont, NY (US); Haigou Huang, Rexford, NY (US); Xusheng Wu, Ballston Lake, NY (US); Ruilong Xie, Niskayuna, NY (US); and Stan Tsai, Clifton Park, NY (US)
Assigned to GLOBALFOUNDRIES Inc., Grand Cayman (KY)
Filed by GLOBALFOUNDRIES Inc., Grand Cayman (KY)
Filed on Oct. 5, 2016, as Appl. No. 15/286,117.
Int. Cl. H01L 21/8234 (2006.01); H01L 21/02 (2006.01); H01L 29/66 (2006.01); H01L 21/311 (2006.01); H01L 21/3105 (2006.01)
CPC H01L 21/823437 (2013.01) [H01L 21/0217 (2013.01); H01L 21/02164 (2013.01); H01L 21/31056 (2013.01); H01L 21/31144 (2013.01); H01L 29/66545 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A method, comprising:
forming a plurality of laterally spaced apart continuous line-type gates above a semiconductor substrate, each of said gates comprising a gate structure and a first layer of a first insulating material positioned on an upper surface of said gate structure;
forming a second layer of a second insulating material above a third insulating material positioned above said substrate between said laterally spaced apart gates, wherein said first insulating material and said second insulating material are selectively etchable relative to one another;
performing at least one first etching process to selectively remove a portion of said first layer relative to portions of said second layer so as to thereby expose a portion of an axial length of said gate structure of at least one of said plurality of gates;
performing at least one second etching process to selectively remove said exposed axial portion of said gate structure of said at least one of said plurality of gates so as to thereby define a gate-cut cavity; and
forming an insulating gate-cut structure in said gate-cut cavity.