US 9,812,364 B2
Method of fabricating semiconductor device with an overlay mask pattern
Jong-Su Kim, Seoul (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si, Gyeonggi-Do (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si, Gyeonggi-Do (KR)
Filed on Jun. 16, 2016, as Appl. No. 15/184,315.
Claims priority of provisional application 62/247,243, filed on Oct. 28, 2015.
Prior Publication US 2017/0125300 A1, May 4, 2017
Int. Cl. H01L 21/8234 (2006.01); H01L 21/02 (2006.01); H01L 21/308 (2006.01); H01L 21/311 (2006.01); H01L 21/3105 (2006.01); H01L 23/544 (2006.01)
CPC H01L 21/823431 (2013.01) [H01L 21/02532 (2013.01); H01L 21/3081 (2013.01); H01L 21/3086 (2013.01); H01L 21/31051 (2013.01); H01L 21/31111 (2013.01); H01L 21/823437 (2013.01); H01L 23/544 (2013.01); H01L 2223/54426 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of fabricating a semiconductor device, comprising:
forming a target layer;
forming a hard mask layer on the target layer;
patterning the hard mask layer to form an overlay mask pattern including a first mask pattern and a plateau-shaped mask pattern, wherein the first mask pattern encloses the plateau-shaped mask pattern and the first mask pattern is spaced apart from the plateau-shaped mask pattern;
patterning the target layer using the overlay mask pattern to form a redundant fin and a plateau-shaped overlay mark; and
removing the redundant fin.