US 9,812,356 B2
Method for manufacturing a semiconductor device
Sung Wook Hwang, Gyeongsangbuk-do (KR); Jong Hyun Lee, Suwon-si (KR); Jae Seok Yang, Hwaseong-si (KR); In Wook Oh, Suwon-si (KR); and Hyun Jae Lee, Seoul (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si, Gyeonggi-Do (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si, Gyeonggi-do (KR)
Filed on Jan. 13, 2017, as Appl. No. 15/405,762.
Claims priority of application No. 10-2016-0033139 (KR), filed on Mar. 21, 2016.
Prior Publication US 2017/0271204 A1, Sep. 21, 2017
Int. Cl. H01L 23/528 (2006.01); H01L 21/768 (2006.01); G06F 17/50 (2006.01)
CPC H01L 21/76879 (2013.01) [G06F 17/5072 (2013.01); H01L 21/76804 (2013.01); H01L 21/76826 (2013.01); H01L 21/76832 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method for manufacturing a semiconductor device, comprising:
generating a layout including a first conductive pattern region and a second conductive pattern region spaced apart from each other in a first direction;
forming a first interlayer insulating film on a substrate, the first interlayer insulating film comprising a first region corresponding to the first conductive pattern region, a second region corresponding to the second conductive pattern region, and a third region spaced apart from the first and second regions, wherein the third region is disposed between the first and second regions;
forming a first block pattern and a second block pattern on the first interlayer insulating film, the first block pattern being disposed between the first region and the third region, and the second block pattern being disposed between the second region and the third region;
partially removing the first interlayer insulating film using the first block pattern and the second block pattern as a mask to form a first recess in the first region, a second recess in the second region, and a third recess in the third region;
forming first, second and third lower metal wirings that respectively fill the first, second and third recesses;
forming a second interlayer insulating film on the first interlayer insulating film; and
forming a first dummy via hole in the second interlayer insulating film, the first dummy via hole exposing a top surface of the third lower metal wiring, wherein the first dummy via hole does not overlap the first lower metal wiring and the second lower metal wiring,
wherein the layout does not include a conductive pattern region corresponding to the third region,
the third lower metal wiring is electrically isolated, and
a distance between the first lower metal wiring and the second lower metal wiring is greater than a sum of a width of the first block pattern, a width of the second block pattern and a width of the first dummy via hole.
 
8. A method for manufacturing a semiconductor device, comprising:
generating a layout including a first conductive pattern region, a second conductive pattern region, a third conductive pattern region and a fourth conductive pattern region, the first conductive pattern region and the second conductive pattern region being spaced apart from each other in a first direction, and the third conductive pattern region and the fourth conductive pattern region being spaced apart from the first conductive pattern region and the second conductive pattern region in a second direction crossing the first direction, wherein the third and fourth conductive pattern regions are spaced part from each other in the first direction;
forming a first interlayer insulating film on a substrate;
forming a first protrusion, a second protrusion, a third protrusion and a fourth protrusion on the first interlayer insulating film, the second protrusion being spaced apart from the first protrusion in the first direction, the fourth protrusion being spaced apart from the third protrusion in the first direction, wherein the third protrusion and the fourth protrusion are spaced apart from the first protrusion and the second protrusion in the second direction;
forming a first lower metal wiring, a second lower metal wiring, a third lower metal wiring, a fourth lower metal wiring, a fifth lower metal wiring and a sixth lower metal wiring on the first interlayer insulating film, the first lower metal wiring corresponding to the first conductive pattern region, the second lower metal wiring corresponding to the second conductive pattern region, the fourth lower metal wiring corresponding to the third conductive pattern region, the fifth lower metal wiring corresponding to the fourth conductive pattern region, wherein the third lower metal wiring is disposed between the first protrusion and the second protrusion and the sixth lower metal wiring is disposed between the third protrusion and the fourth protrusion;
forming a second interlayer insulating film on the first interlayer insulating film; and
forming a first dummy via hole in the second interlayer insulating film, the first dummy via hole exposing a top surface of the third lower metal wiring, wherein the first dummy via hole does not overlap the first lower metal wiring and the second lower metal wiring,
wherein the third lower metal wiring and the sixth lower metal wiring do not conduct electricity,
each of the third lower metal wiring and the sixth lower metal wiring is electrically isolated, and
a distance between the first lower metal wiring and the second lower metal wiring is greater than a sum of a width of the first protrusion, a width of the second protrusion and a width of the first dummy via hole.
 
16. A method for manufacturing a semiconductor device, comprising:
generating a layout of the semiconductor device, the layout including a first region, a second region and a third region spaced apart from each other in a first direction, wherein the third region is disposed between the first and second regions;
forming a first interlayer insulating film on a substrate;
forming a first recess in a first area of the first interlayer insulating film corresponding to the first region, forming a second recess in a second area of the first interlayer insulating film corresponding to the second region, and forming a third recess in a third area of the first interlayer insulating film corresponding to the third region;
forming first, second and third lower metal wirings respectively filling the first, second and third recesses;
forming a second interlayer insulating film on the first interlayer insulating film to cover the first, second and third lower metal wirings;
forming a first trench on the second interlayer insulating film, the first trench including a first dummy via hole which exposes the third lower metal wiring, wherein the first dummy via hole does not overlap the first lower metal wiring and the second lower metal wiring; and
forming a first upper metal wiring to fill the first trench and the first dummy via hole, wherein the first upper metal wiring is electrically connected with the third lower metal wiring through the first dummy via hole,
wherein the third lower metal wiring does not conduct electricity, and
wherein a distance in the first direction between the first lower metal wiring and the second lower metal wiring is greater than a sum of a width of a first block pattern in the first direction, a width of a second block pattern in the first direction and a width of the first dummy via hole in the first direction.