US 9,812,337 B2
Integrated circuit package pad and methods of forming
Hsien-Wei Chen, Hsin-Chu (TW); Chen-Hua Yu, Hsin-Chu (TW); Chi-Hsi Wu, Hsin-Chu (TW); Der-Chyang Yeh, Hsin-Chu (TW); An-Jhih Su, Bade (TW); and Wei-Yu Chen, Hsin-Chu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu (TW)
Filed on Jun. 18, 2015, as Appl. No. 14/743,451.
Claims priority of provisional application 62/087,090, filed on Dec. 3, 2014.
Prior Publication US 2016/0163566 A1, Jun. 9, 2016
Int. Cl. H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 23/31 (2006.01); H01L 23/498 (2006.01); H01L 25/10 (2006.01); H01L 23/00 (2006.01); H01L 25/00 (2006.01); H01L 23/538 (2006.01); H01L 25/065 (2006.01)
CPC H01L 21/4846 (2013.01) [H01L 21/486 (2013.01); H01L 21/565 (2013.01); H01L 21/568 (2013.01); H01L 23/3128 (2013.01); H01L 23/3185 (2013.01); H01L 23/498 (2013.01); H01L 23/49838 (2013.01); H01L 24/19 (2013.01); H01L 24/20 (2013.01); H01L 25/105 (2013.01); H01L 25/50 (2013.01); H01L 23/49827 (2013.01); H01L 23/5389 (2013.01); H01L 25/0657 (2013.01); H01L 2224/04105 (2013.01); H01L 2224/12105 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48227 (2013.01); H01L 2224/73265 (2013.01); H01L 2224/73267 (2013.01); H01L 2224/83005 (2013.01); H01L 2224/92244 (2013.01); H01L 2225/0651 (2013.01); H01L 2225/06568 (2013.01); H01L 2225/1035 (2013.01); H01L 2225/1041 (2013.01); H01L 2225/1058 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/181 (2013.01); H01L 2924/18162 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of manufacturing a semiconductor device, the method comprising:
forming a first layer over a carrier substrate;
forming a second layer over the first layer;
forming a conductive structure on the second layer;
placing an integrated circuit die over the first layer, the integrated circuit die having contact pads facing away from the carrier substrate;
forming a molding compound over the first layer, the molding compound extending along sidewalls of the integrated circuit die and the conductive structure, thereby forming a through via, wherein the through via comprises a through via projection, the through via projection extending through the second layer;
removing the carrier substrate, exposing the first layer; and
completely removing the first layer, thereby exposing the through via.