US 9,812,336 B2
FinFET semiconductor structures and methods of fabricating same
Michael Ganz, Clifton Park, NY (US); Bingwu Liu, Ballston Spa, NY (US); Johannes Marinus Van Meer, Delmar, NY (US); and Sruthi Muralidharan, Troy, NY (US)
Assigned to GLOBALFOUNDRIES INC., Grand Cayman (KY)
Filed by GLOBALFOUNDRIES Inc., Grand Cayman (KY)
Filed on Oct. 21, 2014, as Appl. No. 14/519,215.
Claims priority of provisional application 61/896,989, filed on Oct. 29, 2013.
Prior Publication US 2015/0115371 A1, Apr. 30, 2015
Int. Cl. H01L 21/02 (2006.01); H01L 21/266 (2006.01); H01L 29/78 (2006.01); H01L 21/324 (2006.01); H01L 29/66 (2006.01); H01L 21/265 (2006.01); H01L 21/3213 (2006.01); H01L 21/268 (2006.01)
CPC H01L 21/324 (2013.01) [H01L 21/265 (2013.01); H01L 21/266 (2013.01); H01L 29/66803 (2013.01); H01L 29/7854 (2013.01); H01L 21/268 (2013.01); H01L 21/32139 (2013.01)] 3 Claims
OG exemplary drawing
 
1. A method of forming a semiconductor structure comprising:
providing an intermediate semiconductor structure, comprising:
a semiconductor substrate;
a fin having an extended gate (EG) oxide layer in contact with at least a portion of the fin; and
a gate material disposed over the fin;
forming, over the fin and gate material of the intermediate semiconductor structure, a gate stack hardmask comprising an oxide layer;
forming, prior to gate etch processing to define gate regions, a silicon nitride barrier layer on the oxide layer of the gate stack hardmask;
performing one or more gate stack hardmask patterning steps, comprising forming, directly on the silicon nitride barrier layer, an organic planarizing layer (OPL);
removing the EG oxide layer from portions of the fin that are not located under the gate; and
subsequent to removing the EG oxide layer from portions of the fin that are not located under the gate, performing one or more ion implantation steps.