US 9,812,328 B2
Methods for forming low resistivity interconnects
Kaushal K. Singh, Santa Clara, CA (US); Er-Xuan Ping, Fremont, CA (US); Xianmin Tang, San Jose, CA (US); Sundar Ramamurthy, Fremont, CA (US); and Randhir Thakur, Fremont, CA (US)
Assigned to APPLIED MATERIALS, INC., Santa Clara, CA (US)
Filed by Applied Materials, Inc., Santa Clara, CA (US)
Filed on Jun. 22, 2016, as Appl. No. 15/189,768.
Claims priority of provisional application 62/182,925, filed on Jun. 22, 2015.
Prior Publication US 2016/0372371 A1, Dec. 22, 2016
Int. Cl. H01L 21/4763 (2006.01); H01L 21/285 (2006.01); H01L 23/485 (2006.01); H01L 23/532 (2006.01)
CPC H01L 21/28518 (2013.01) [H01L 23/485 (2013.01); H01L 23/53209 (2013.01); H01L 23/53219 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A silicide formation method, comprising:
depositing one or more first layers on a silicon containing substrate, wherein the one or more first layers comprise a transition metal aluminum alloy layer;
depositing a second layer comprising a transition metal on the one or more first layers, wherein a thickness of the second layer is between about 25 nm and about 75 nm; and
performing an annealing process after depositing the second layer at a temperature of less than about 500° C. to form a silicide material, wherein the silicide material has a thickness at least two times greater than the thickness of the second layer.