US 9,812,323 B2
Low external resistance channels in III-V semiconductor devices
Effendi Leobandung, Stormville, NY (US); and Yanning Sun, Scarsdale, NY (US)
Assigned to Internaitonal Business Machines Corporation, Armonk, NY (US)
Filed by International Business Machines Corporation, Armonk, NY (US)
Filed on Sep. 8, 2014, as Appl. No. 14/479,504.
Prior Publication US 2016/0071968 A1, Mar. 10, 2016
Int. Cl. H01L 21/338 (2006.01); H01L 21/02 (2006.01); H01L 29/08 (2006.01); H01L 29/10 (2006.01); H01L 29/66 (2006.01); H01L 29/778 (2006.01); H01L 29/205 (2006.01)
CPC H01L 21/02546 (2013.01) [H01L 29/0847 (2013.01); H01L 29/1054 (2013.01); H01L 29/66545 (2013.01); H01L 29/7781 (2013.01); H01L 29/205 (2013.01)] 3 Claims
OG exemplary drawing
 
1. A structure comprising:
a III-V compound semiconductor substrate comprising a substrate layer, a further III-V compound semiconductor material layer on top a surface of said substrate layer, and a doped III-V compound semiconductor material layer on top a surface of said further III-V compound semiconductor material layer, said doped III-V compound semiconductor material layer having a first conductivity type dopant;
a III-V compound semiconductor material replacement channel formed in the doped III-V compound semiconductor material layer of the III-V compound semiconductor substrate, said replacement channel extending for a length defined by first and second sidewalls, and a top surface and a bottom surface of the III-V compound semiconductor material replacement channel is co-planar with a respective top surface and a bottom surface of the doped III-V compound semiconductor material layer, said replacement channel having a second conductivity type dopant opposite said first conductivity type;
a gate stack on a surface of the replacement channel, the gate stack having respective first and second sidewalls that is each substantially in alignment with a respective first and second sidewall of the replacement channel;
a gate spacer on the doped III-V compound semiconductor material layer, the gate spacer having respective first inner and second inner sidewall surfaces adjacent to and contacting the respective first and second sidewall of the gate stack wherein a first inner sidewall surface and second inner sidewall surface of the gate spacer is aligned with said defined first and second sidewalls of said replacement channel;
a raised source-drain (RSD) region on the doped layer, the RSD region adjacent to and contacting the gate spacer; and
an insulator layer on the RSD region, the insulator layer adjacent to and contacting the gate spacer.