US 9,812,317 B2
Semiconductor device and method of manufacturing the same
Yusuke Terada, Tokyo (JP); Shigeya Toyokawa, Tokyo (JP); and Atsushi Maeda, Tokyo (JP)
Assigned to Renesas Electronics Corporation, Tokyo (JP)
Filed by Renesas Electronics Corporation, Tokyo (JP)
Filed on Jan. 4, 2017, as Appl. No. 15/397,800.
Application 15/397,800 is a continuation of application No. 14/876,284, filed on Oct. 6, 2015, granted, now 9,601,433.
Application 14/876,284 is a continuation of application No. 14/616,955, filed on Feb. 9, 2015, granted, now 9,184,126, issued on Nov. 10, 2015.
Application 14/616,955 is a continuation of application No. 14/060,464, filed on Oct. 22, 2013, granted, now 8,975,127, issued on Mar. 10, 2015.
Application 14/060,464 is a continuation of application No. 13/281,454, filed on Oct. 26, 2011, granted, now 8,604,526, issued on Dec. 10, 2013.
Application 13/281,454 is a continuation of application No. 12/133,362, filed on Jun. 4, 2008, granted, now 8,072,035, issued on Dec. 6, 2011.
Claims priority of application No. 2007-153840 (JP), filed on Jun. 11, 2007; and application No. 2008-71291 (JP), filed on Mar. 19, 2008.
Prior Publication US 2017/0117143 A1, Apr. 27, 2017
Int. Cl. H01L 21/02 (2006.01); H01L 21/762 (2006.01); H01L 21/768 (2006.01); H01L 21/3105 (2006.01); H01L 29/66 (2006.01); G02F 1/1362 (2006.01); G02F 1/1333 (2006.01); G02F 1/1343 (2006.01); H01L 27/12 (2006.01); G02F 1/133 (2006.01); G02F 1/1368 (2006.01)
CPC H01L 21/02274 (2013.01) [G02F 1/13439 (2013.01); G02F 1/133345 (2013.01); G02F 1/134309 (2013.01); G02F 1/136286 (2013.01); H01L 21/31051 (2013.01); H01L 21/76224 (2013.01); H01L 21/76895 (2013.01); H01L 29/6675 (2013.01); G02F 1/1368 (2013.01); G02F 1/13306 (2013.01); G02F 2001/133302 (2013.01); G02F 2001/136295 (2013.01); H01L 27/124 (2013.01)] 10 Claims
OG exemplary drawing
 
1. A manufacturing method of a semiconductor device including a MISFET, comprising steps of:
(a) selectively forming a first insulating film in a semiconductor substrate;
(b) forming an impurity region as a source region or a drain region of the MISFET in the semiconductor substrate such that the impurity region contains the first insulating film;
(c) forming a gate insulating film of the MISFET over the semiconductor substrate;
(d) forming a gate electrode of the MISFET over the gate insulating film and the first insulating film such that an edge of the gate electrode is located over the first insulating film in a gate length direction;
(e) after the step (d), forming a second insulating film covering the MISFET;
(f) forming a third insulating film over the second insulating film;
(g) planarizing at least a surface of the third insulating film;
(h) after the step (g), forming a fourth insulating film over the third insulating film;
(i) forming a first plug in the fourth, third and second insulating films in order to reach the impurity region; and
(j) forming a first wire over the fourth insulating film in order to be connected with the first plug,
wherein the second insulating film is formed by using a first plasma,
wherein the third insulating film is formed by using a second plasma, and
wherein a density of the first plasma is higher than a density of the second plasma.