US 9,812,223 B2
Semiconductor memory device and method of operating the same
Tae Hoon Kim, Gyeonggi-do (KR)
Assigned to SK Hynix Inc., Gyeonggi-do (KR)
Filed by SK hynix Inc., Gyeonggi-do (KR)
Filed on Jul. 15, 2016, as Appl. No. 15/211,779.
Application 15/211,779 is a continuation in part of application No. 14/292,299, filed on May 30, 2014, granted, now 9,406,402.
Claims priority of application No. 10-2013-0071659 (KR), filed on Jun. 21, 2013.
Prior Publication US 2016/0329105 A1, Nov. 10, 2016
Int. Cl. G11C 29/50 (2006.01); G11C 11/56 (2006.01); G11C 16/34 (2006.01); G11C 16/24 (2006.01); G11C 16/26 (2006.01)
CPC G11C 29/50004 (2013.01) [G11C 11/5642 (2013.01); G11C 16/24 (2013.01); G11C 16/26 (2013.01); G11C 16/3418 (2013.01); G11C 2029/5004 (2013.01)] 11 Claims
OG exemplary drawing
 
1. A semiconductor memory device, comprising;
memory cells coupled to a word line; and
a peripheral circuit configured to read first to kth page data from the memory cells by sequentially applying first to kth test voltages, to the word line, where k is a natural number greater than 3,
wherein the first to kth test voltages are sequentially increased, and respective application times of the first to kth test voltages applied to the word line are sequentially reduced.