US 9,812,221 B1
Multi-core cache coherency built-in test
John L. Hagen, Marion, IA (US); David J. Radack, Robins, IA (US); Lloyd F. Aquino, Marion, IA (US); and Todd E. Miller, Marion, IA (US)
Assigned to Rockwell Collins, Inc., Cedar Rapids, IA (US)
Filed by John L. Hagen, Marion, IA (US); David J. Radack, Robins, IA (US); Lloyd F. Aquino, Marion, IA (US); and Todd E. Miller, Marion, IA (US)
Filed on Sep. 9, 2015, as Appl. No. 14/849,390.
Int. Cl. G06F 12/08 (2016.01); G11C 29/38 (2006.01); G11C 29/36 (2006.01); G06F 12/0891 (2016.01); G06F 12/0815 (2016.01)
CPC G11C 29/38 (2013.01) [G06F 12/0815 (2013.01); G06F 12/0891 (2013.01); G11C 29/36 (2013.01); G06F 2212/1032 (2013.01); G06F 2212/50 (2013.01); G06F 2212/62 (2013.01); G06F 2212/682 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A processor system comprising:
at least one system health monitor (HM);
a multi-core processor (MCP) including one or more processor cores, each processor core having a core status, the MCP configured to designate the core status of a first processor core as a primary core, and to designate the core status of at least one second processor core as a secondary core;
a first cache coupled to the first processor core;
at least one second cache coupled to the at least one second processor core;
at least one third cache couplable to the MCP;
at least one system memory couplable to the MCP, the at least one system memory including at least one first data page and at least one control page, the at least one first data page including at least one first memory address and the at least one control page including at least one second memory address;
the primary core configured to
(a) generate at least one first mapping associated with the at least one first data page;
(b) lock at least one first cache line of the first cache;
(c) lock at least one second cache line of the at least one third cache, the at least one first cache line and the at least one second cache line associated with the at least one first data page;
(d) write at least one first data pattern to the at least one first cache line;
(e) perform a first flush of the at least one first cache line;
(f) pass at least one of a first update notification and the at least one first data pattern to the at least one secondary core via the at least one control page; and
(g) if at least one first test fail is received from a secondary core, log at least one first fatal fault via the at least one system HM;
the at least one secondary core configured to
(a) generate at least one second mapping associated with the at least one first data page;
(b) lock at least one third cache line of the at least one second cache, the at least one third cache line associated with the at least one first data page;
(c) on receiving the at least one of a first update notification and the at least one first data pattern, read at least one second data pattern from the at least one third cache line;
(d) determine at least one of a first test pass and a first test fail by comparing the at least one first data pattern and the at least one second data pattern; and
(e) report the at least one of a first test pass and a first test fail to the primary core via the at least one control page.