US 9,812,220 B2
Buffered multi-rank memory modules configured to selectively link rank control signals and methods of operating the same
Tae-Hyung Kim, Seoul (KR); Huichong Shin, Seongnam-si (KR); Seokil Kim, Hwaseong-si (KR); Young Yun, Yongin-si (KR); Jonghyoung Lim, Seoul (KR); and Youkeun Han, Yongin-si (KR)
Assigned to Samsung Electronics Co., Ltd., (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do (KR)
Filed on Jul. 12, 2016, as Appl. No. 15/207,557.
Claims priority of application No. 10-2015-0136181 (KR), filed on Sep. 25, 2015.
Prior Publication US 2017/0092379 A1, Mar. 30, 2017
Int. Cl. G11C 7/10 (2006.01); G11C 29/34 (2006.01); G06F 3/06 (2006.01); G06F 12/1009 (2016.01); G11C 11/4076 (2006.01); G11C 11/4093 (2006.01); G11C 5/04 (2006.01)
CPC G11C 29/34 (2013.01) [G06F 3/0613 (2013.01); G06F 3/0647 (2013.01); G06F 3/0656 (2013.01); G06F 3/0688 (2013.01); G06F 12/1009 (2013.01); G11C 7/109 (2013.01); G11C 7/1045 (2013.01); G06F 2212/1024 (2013.01); G11C 5/04 (2013.01); G11C 11/4076 (2013.01); G11C 11/4093 (2013.01)] 10 Claims
OG exemplary drawing
 
1. A memory module, comprising:
a plurality of semiconductor memory devices on a substrate to provide a dual in-line memory module (DIMM) organized into at least two ranks; and
a memory buffer,
wherein when a parallel bit test operation is started with respect to the plurality of semiconductor memory devices, the memory buffer changes a rank control signal received from a memory controller from inactive to active based on a mapping table defined according to a mode register set signal to perform the parallel bit test operation simultaneously to all the ranks.