US 9,812,219 B2
Automatic test-pattern generation for memory-shadow-logic testing
Nishu Kohli, Noida (IN)
Assigned to STMicroelectronics International N.V., Schiphol (NL)
Filed by STMicroelectronics International N.V., Amsterdam (NL)
Filed on Mar. 6, 2015, as Appl. No. 14/640,601.
Application 14/640,601 is a division of application No. 13/175,530, filed on Jul. 1, 2011, granted, now 9,003,255.
Prior Publication US 2015/0179282 A1, Jun. 25, 2015
Int. Cl. G11C 29/10 (2006.01); G11C 29/24 (2006.01); G11C 29/00 (2006.01); G11C 29/14 (2006.01); G11C 29/54 (2006.01); G11C 29/52 (2006.01); G11C 29/50 (2006.01); G11C 29/56 (2006.01); G11C 11/34 (2006.01); G11C 11/22 (2006.01); G01R 31/3183 (2006.01); G11C 11/4063 (2006.01)
CPC G11C 29/10 (2013.01) [G01R 31/318307 (2013.01); G01R 31/318371 (2013.01); G11C 11/2273 (2013.01); G11C 11/2275 (2013.01); G11C 11/34 (2013.01); G11C 11/4063 (2013.01); G11C 29/00 (2013.01); G11C 29/14 (2013.01); G11C 29/24 (2013.01); G11C 29/50 (2013.01); G11C 29/52 (2013.01); G11C 29/54 (2013.01); G11C 29/56004 (2013.01); G11C 29/56008 (2013.01); G01R 31/318342 (2013.01)] 24 Claims
OG exemplary drawing
 
1. A method for automated test pattern generation (ATPG), the method comprising:
generating a test pattern using respective ATPG memory address locations of a memory coupled to a logic circuit under test, in an ATPG mode of operation;
wherein the generation of the test pattern using the respective ATPG memory address locations produces a voltage differential at inputs to sense amplifiers coupled to the memory that is substantially equal to a voltage differential produced at the inputs to the sense amplifiers by data memory address locations of the memory during a normal mode of operation;
applying the generated test pattern to the logic circuit under test.