| US 9,812,216 B1 | ||
| Circuits and methods for generating a clock enable signal using a shift register | ||
| Kalyana Kantipudi, San Jose, CA (US) | ||
| Assigned to Altera Corporation, San Jose, CA (US) | ||
| Filed by Altera Corporation, San Jose, CA (US) | ||
| Filed on Jun. 29, 2016, as Appl. No. 15/197,442. | ||
| Int. Cl. G01R 31/3173 (2006.01); G11C 19/00 (2006.01); G01R 31/317 (2006.01) | ||
| CPC G11C 19/00 (2013.01) [G01R 31/3173 (2013.01); G01R 31/31704 (2013.01); G01R 31/31727 (2013.01)] | 20 Claims |
| 1. A method comprising:
generating multiple pulses in a clock enable signal using a shift register circuit in response to a single transition in a
start signal and in response to control signals; and
generating an output signal for testing an electronic circuit using a first multiplexer circuit by selecting from an input
signal and a first clock signal, wherein selection of the first multiplexer circuit is controlled by the multiple pulses in
the clock enable signal.
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