US 9,812,215 B2
Memory device that executes an erase operation for a nonvolatile memory
Kazutaka Takizawa, Yokohama (JP); Chao Wang, Kamakura (JP); and Masaaki Niijima, Machida (JP)
Filed by Toshiba Memory Corporation, Minato-ku (JP)
Filed on Sep. 9, 2016, as Appl. No. 15/260,962.
Claims priority of provisional application 62/313,325, filed on Mar. 25, 2016.
Prior Publication US 2017/0278581 A1, Sep. 28, 2017
Int. Cl. G11C 16/16 (2006.01); G11C 16/34 (2006.01); G11C 16/10 (2006.01); G11C 16/26 (2006.01)
CPC G11C 16/3495 (2013.01) [G11C 16/10 (2013.01); G11C 16/16 (2013.01); G11C 16/26 (2013.01); G11C 16/3445 (2013.01)] 20 Claims
OG exemplary drawing
1. A memory device comprising:
a controller; and
a nonvolatile memory in which an erase operation is controlled by the controller, the nonvolatile memory including blocks, each of the blocks being a unit for the erase operation, the nonvolatile memory transferring a first reply showing a completion of the erase operation and first information based on a number of memory cells in which a data erase is uncompleted after the completion of the erase operation to the controller.