US 9,812,214 B2
Nonvolatile memory device, storage device including nonvolatile memory device and operating method of nonvolatile memory device
Dongkyo Shim, Seoul (KR); and Sang-Soo Park, Hwaseong-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Samsung-ro, Yeongtong-gu, Suwon-si, Gyeonggi-do (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Nov. 1, 2016, as Appl. No. 15/340,957.
Claims priority of application No. 10-2015-0153267 (KR), filed on Nov. 2, 2015.
Prior Publication US 2017/0125116 A1, May 4, 2017
Int. Cl. G11C 16/34 (2006.01); G11C 16/08 (2006.01); G11C 16/10 (2006.01); G11C 16/16 (2006.01); G11C 11/56 (2006.01); G11C 16/14 (2006.01); G11C 16/04 (2006.01); G11C 16/26 (2006.01)
CPC G11C 16/3445 (2013.01) [G11C 11/5635 (2013.01); G11C 16/08 (2013.01); G11C 16/10 (2013.01); G11C 16/14 (2013.01); G11C 16/16 (2013.01); G11C 16/0483 (2013.01); G11C 16/26 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A nonvolatile memory device, comprising:
a plurality of memory blocks each comprising a plurality of memory cells;
a row decoder circuit connected to the memory cells through word lines;
a page buffer circuit connected to the memory cells through bit lines; and
a control logic circuit configured to control an erase operation of memory cells in a first memory block selected from the memory blocks,
wherein the erase operation comprises iteratively performing an erase loop which comprises an erase section in which an erase voltage is applied to the memory cells of the first memory block and an erase verification section in which the memory cells of the first memory block are verified using a first read voltage,
wherein the control logic circuit is configured such that if the memory cells of the first memory block are determined as an erase pass in the erase verification section, the control logic circuit controls a read of the memory cells of the first memory block using a second read voltage different from the first read voltage,
wherein the control logic circuit is configured to apply an extra erase voltage to the memory cells of the first memory block based on a result of the read of the memory cells of the first memory block using the second read voltage, and
wherein the nonvolatile memory device is configured such that threshold voltages of the memory cells of the first memory block when the extra erase voltage is applied to the memory cells of the first memory block are lower than corresponding threshold voltages of the memory cells of the first memory block when an erase voltage of a most recent previous erase loop is applied to the memory cells of the first memory block.