US 9,812,212 B2
Memory cell with low reading voltages
Hsueh-Wei Chen, Hsinchu (TW); Wei-Ren Chen, Pingtung County (TW); and Wein-Town Sun, Taoyuan (TW)
Assigned to eMemory Technology Inc., Hsin-Chu (TW)
Filed by eMemory Technology Inc., Hsin-Chu (TW)
Filed on Jan. 18, 2017, as Appl. No. 15/408,434.
Claims priority of provisional application 62/280,683, filed on Jan. 19, 2016.
Prior Publication US 2017/0206975 A1, Jul. 20, 2017
Int. Cl. G11C 16/04 (2006.01); G11C 16/26 (2006.01); G11C 16/14 (2006.01); H01L 27/11519 (2017.01)
CPC G11C 16/26 (2013.01) [G11C 16/0408 (2013.01); G11C 16/14 (2013.01); H01L 27/11519 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory cell comprising:
a program select transistor having a first terminal coupled to a program source line, a second terminal, a control terminal coupled to a program select line, and a body terminal coupled to a program control line;
a program element having a first terminal coupled to the second terminal of the program select transistor, a second terminal coupled to a program bit line, and a body terminal coupled to the program control line;
a read select transistor having a first terminal coupled to a read source line, a second terminal, a control terminal coupled to a read select line, and a body terminal coupled to a bias control line;
a read element having a first terminal coupled to the second terminal of the read select transistor, a second terminal coupled to a read bit line, and a body terminal coupled to the bias control line;
a common floating gate coupled to the program element and the read element; and
an erase element having a first terminal coupled to an erase control line, and a second terminal coupled to the common floating gate;
wherein a thickness of a gate oxide of the read select transistor is smaller than a thickness of a gate oxide of the program select transistor.