US 9,812,211 B2
Semiconductor device
Toshihiro Tanaka, Akiruno (JP); Yukiko Umemoto, Kodaira (JP); Mitsuru Hiraki, Kodaira (JP); Yutaka Shinagawa, Iruma (JP); Masamichi Fujito, Kodaira (JP); Kazufumi Suzukawa, Ichikawa (JP); Hiroyuki Tanikawa, Akishima (JP); Takashi Yamaki, Kodaira (JP); Yoshiaki Kamigaki, Takamatsu (JP); Shinichi Minami, Kodaira (JP); Kozo Katayama, Tokyo (JP); and Nozomu Matsuzaki, Kokubunji (JP)
Assigned to Renesas Electronics Corporation, Tokyo (JP)
Filed by Renesas Electronics Corporation, Koutou-ku, Tokyo (JP)
Filed on Aug. 1, 2016, as Appl. No. 15/224,669.
Application 15/224,669 is a continuation of application No. 14/214,969, filed on Mar. 16, 2014, granted, now 9,412,459.
Application 14/214,969 is a continuation of application No. 13/867,055, filed on Apr. 20, 2013, granted, now 8,698,224, issued on Apr. 15, 2014.
Application 13/867,055 is a continuation of application No. 13/223,380, filed on Sep. 1, 2011, granted, now 8,426,904, issued on Apr. 23, 2013.
Application 13/223,380 is a continuation of application No. 12/718,111, filed on Mar. 5, 2010, granted, now 8,017,986, issued on Sep. 13, 2011.
Application 12/718,111 is a continuation of application No. 12/142,566, filed on Jun. 19, 2008, granted, now 7,700,992, issued on Apr. 20, 2010.
Application 12/142,566 is a continuation of application No. 11/415,129, filed on May 2, 2006, granted, now 7,414,283, issued on Aug. 19, 2008.
Application 11/415,129 is a continuation of application No. 10/484,578, granted, now 7,057,230, issued on Jun. 6, 2006, previously published as PCT/JP02/07371, filed on Jul. 22, 2002.
Claims priority of application No. 2001-227203 (JP), filed on Jul. 27, 2001; and application No. 2001-228870 (JP), filed on Jul. 30, 2001.
Prior Publication US 2016/0336074 A1, Nov. 17, 2016
Int. Cl. G11C 16/10 (2006.01); G11C 16/26 (2006.01); H01L 21/28 (2006.01); H01L 27/105 (2006.01); H01L 27/115 (2017.01); H01L 27/11521 (2017.01); H01L 27/11526 (2017.01); H01L 27/11546 (2017.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/788 (2006.01); H01L 29/792 (2006.01); G11C 16/24 (2006.01); G11C 5/02 (2006.01); G11C 8/08 (2006.01); G11C 16/08 (2006.01); G11C 16/30 (2006.01); G11C 16/04 (2006.01)
CPC G11C 16/26 (2013.01) [G11C 5/025 (2013.01); G11C 8/08 (2013.01); G11C 16/04 (2013.01); G11C 16/0433 (2013.01); G11C 16/08 (2013.01); G11C 16/24 (2013.01); G11C 16/30 (2013.01); H01L 21/28 (2013.01); H01L 21/28273 (2013.01); H01L 27/105 (2013.01); H01L 27/115 (2013.01); H01L 27/11521 (2013.01); H01L 27/11526 (2013.01); H01L 27/11546 (2013.01); H01L 29/4234 (2013.01); H01L 29/42328 (2013.01); H01L 29/42332 (2013.01); H01L 29/66825 (2013.01); H01L 29/7885 (2013.01); H01L 29/792 (2013.01); G11C 16/0425 (2013.01)] 6 Claims
OG exemplary drawing
 
1. A flash memory module comprising:
a first driver circuit including a plurality of first drivers, and selecting one of the first drivers;
a second driver circuit coupled to the first driver circuit and including a plurality of second drivers, the second driver circuit selecting one of the second drivers based on an output state of the selected first driver; and
a writing control circuit which latches read data based on the selected first driver and the selected second driver upon a write operation, and which selects the latched data upon a read operation.