US 9,812,209 B2
System and method for memory integrated circuit chip write abort indication
Asaf Gueta, Or-Yehuda (IL); Inon Cohen, Oranit (IL); and Arie Star, Hadera (IL)
Assigned to SanDisk Technologies LLC, Plano, TX (US)
Filed by SanDisk Technologies LLC, Plano, TX (US)
Filed on May 2, 2017, as Appl. No. 15/584,339.
Application 15/584,339 is a division of application No. 14/718,488, filed on May 21, 2015, granted, now 9,659,619.
Prior Publication US 2017/0236590 A1, Aug. 17, 2017
Int. Cl. G11C 16/04 (2006.01); G11C 16/22 (2006.01); G11C 7/24 (2006.01); G11C 16/10 (2006.01); G11C 16/14 (2006.01); G06F 13/16 (2006.01); G11C 16/30 (2006.01)
CPC G11C 16/225 (2013.01) [G06F 13/1668 (2013.01); G11C 7/24 (2013.01); G11C 16/10 (2013.01); G11C 16/105 (2013.01); G11C 16/14 (2013.01); G11C 16/22 (2013.01); G11C 16/30 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory device controller comprising:
memory integrated circuit chip inquiry circuitry configured to send an inquiry to a memory integrated circuit chip, the inquiry indicative of requesting the memory integrated circuit chip to send one or more flag values and the associated addresses, the one or more flag values indicative of execution of a command at the associated addresses by the memory integrated circuit chip; and
abort identification circuitry configured to identify, based on the one or more flag values and the associated addresses, a section of memory within the memory integrated circuit chip containing valid data resulting from proper execution of the command or invalid data resulting from aborted execution of the command.