| US 9,812,207 B2 | ||
| Semiconductor memory device | ||
| Takeshi Hioka, Machida (JP) | ||
| Assigned to TOSHIBA MEMORY CORPORATION, Minato-ku (JP) | ||
| Filed by TOSHIBA MEMORY CORPORATION, Minato-ku (JP) | ||
| Filed on Mar. 13, 2017, as Appl. No. 15/457,137. | ||
| Application 15/457,137 is a continuation of application No. 14/849,082, filed on Sep. 9, 2015, granted, now 9,633,730. | ||
| Claims priority of application No. 2015-049724 (JP), filed on Mar. 12, 2015. | ||
| Prior Publication US 2017/0186488 A1, Jun. 29, 2017 | ||
| Int. Cl. G11C 16/04 (2006.01); G11C 16/26 (2006.01) | ||
| CPC G11C 16/0483 (2013.01) [G11C 16/26 (2013.01)] | 18 Claims |
| 1. A semiconductor memory device comprising:
a first string comprising a first transistor coupled to a bit line, a second transistor coupled to a source line, and first
cell transistors serially-coupled between the first transistor and the second transistor;
a second string comprising a third transistor coupled to the bit line, a fourth transistor coupled to the source line, and
second cell transistors serially-coupled between the third transistor and the fourth transistor, a gate of the first transistor
being separate from a gate of the third transistor, a gate of the second transistor being coupled to a gate of the fourth
transistor; and
a control circuit configured to apply a first voltage to the source line, a second voltage to the bit line, a third voltage
to the gate of the second transistor, a fourth voltage to a gate of a first one of the first cell transistors, and a fifth
voltage to a gate of a second one of the first cell transistors during a read, the first voltage being higher than the second
voltage, the first voltage being substantially the same as the third voltage, and the fifth voltage being higher than the
fourth voltage.
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