US 9,812,206 B2
3D flash memory device having different dummy word lines and data storage devices including same
Sang-Wan Nam, Hwaseong-si (KR); and Kitae Park, Seongnam-si (KR)
Assigned to Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do (KR)
Filed by Sang-Wan Nam, Hwaseong-si (KR); and Kitae Park, Seongnam-si (KR)
Filed on Jan. 24, 2014, as Appl. No. 14/162,905.
Claims priority of application No. 10-2013-0053212 (KR), filed on May 10, 2013.
Prior Publication US 2014/0334232 A1, Nov. 13, 2014
Int. Cl. G11C 11/34 (2006.01); G11C 16/04 (2006.01); G11C 16/16 (2006.01); G11C 16/34 (2006.01); G11C 16/08 (2006.01); G11C 16/10 (2006.01)
CPC G11C 16/0483 (2013.01) [G11C 16/08 (2013.01); G11C 16/10 (2013.01); G11C 16/16 (2013.01); G11C 16/3427 (2013.01)] 14 Claims
OG exemplary drawing
 
1. A three-dimensional (3D) flash memory device having a plurality of cell strings arranged in a direction perpendicular to a substrate, the 3D flash memory device comprising:
a first cell string connected between a bit line and a common source line and including a program cell;
a second cell string connected between the bit line and the common source line and including a program inhibit cell connected to a same word line as the program cell;
a first string select line that selects the first cell string and a second string select line that selects the second cell string;
a first dummy word line disposed between a ground select line and a lowermost main word line;
a second dummy word line having a different word line configuration than the first dummy word line and disposed between the first and second string select lines and an uppermost main word line,
wherein the first and second string select lines, the first and second dummy word lines, the ground select line, the lowermost main word line and the uppermost main word line are connected to the first and second cell strings, and
wherein the first dummy word line comprises a first number of word lines and the second dummy word line comprises a second number of word lines different from the first number; and
an address decoder configured during an erase operation to connect a first erase voltage from among a plurality of different erase voltages to one of the first number of word lines adjacent to the lowermost main word line, and a second erase voltage from among the plurality of different erase voltages to another one of the first number of word lines adjacent to the ground select line, wherein a level of the first erase voltage is greater than a level of the second erase voltage.