US 9,812,205 B2
MTJ-based content addressable memory with measured resistance across matchlines
Swaroop Ghosh, Tampa, FL (US); and Cheng Wei Lin, Seffner, FL (US)
Assigned to UNIVERSITY OF SOUTH FLORIDA, Tampa, FL (US)
Filed by Swaroop Ghosh, Tampa, FL (US); and Cheng Wei Lin, Seffner, FL (US)
Filed on Jul. 8, 2016, as Appl. No. 15/205,813.
Claims priority of provisional application 62/192,794, filed on Jul. 15, 2015.
Prior Publication US 2017/0018308 A1, Jan. 19, 2017
Int. Cl. G11C 15/00 (2006.01); G11C 15/04 (2006.01); G11C 15/02 (2006.01); G11C 11/16 (2006.01)
CPC G11C 15/046 (2013.01) [G11C 15/02 (2013.01); G11C 11/1675 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A content addressable memory cell apparatus, comprising:
a plurality of domain-wall-based magnetic tunnel junctions (DW-MTJs) interconnected to write complementary bits, wherein a write polarity on each of the plurality of DW-MTJs is controlled by modulating a direction of current;
a plurality of transistors;
a plurality of searchlines;
a wordline;
a bitline (BL);
a sourceline (SrL); and
a plurality of matchlines.