US 9,812,204 B1
Ferroelectric memory cell without a plate line
Tianhong Yan, Saratoga, CA (US); and Yung-Tin Chen, Santa Clara, CA (US)
Assigned to AUCMOS Technologies USA, Inc., Santa Clara, CA (US)
Filed by AUCMOS Technologies USA, Inc., Santa Clara, CA (US)
Filed on Dec. 28, 2016, as Appl. No. 15/391,982.
Claims priority of provisional application 62/414,530, filed on Oct. 28, 2016.
Int. Cl. G11C 11/00 (2006.01); G11C 14/00 (2006.01); H01L 27/11 (2006.01); H01L 27/11502 (2017.01)
CPC G11C 14/0072 (2013.01) [H01L 27/1104 (2013.01); H01L 27/11502 (2013.01)] 4 Claims
OG exemplary drawing
 
1. A ferroelectric static random access memory (FeSRAM) cell, capable of operating under a static random access memory (SRAM) phase and a ferroelectric capacitor programming phase, comprising:
first and second cross-coupled inverters connected between a power supply voltage signal and a ground reference voltage signal and holding a data signal represented in a complementary manner in first and second common data terminals;
first and second select transistors coupled respectively to the first and second common data terminals of the cross-coupled inverters; and
first, second, third and fourth ferroelectric capacitors, wherein, during the SRAM phase, the first and second ferroelectric capacitors couple the first common data terminal to the power supply voltage signal and the ground reference voltage signal, respectively, and wherein the third and the fourth ferroelectric capacitors couple the second common data terminal to the power supply voltage signal and the ground reference voltage signal, respectively.