US 9,812,203 B2
Semiconductor memory having both volatile and non-volatile functionality including resistance change material and method of operating
Yuniarto Widjaja, San Jose, CA (US)
Assigned to Zeno Semiconductor, Inc., Sunnyvale, CA (US)
Filed by Zeno Semiconductor, Inc., Sunnyvale, CA (US)
Filed on Oct. 12, 2016, as Appl. No. 15/292,098.
Application 14/738,349 is a division of application No. 13/244,812, filed on Sep. 26, 2011, granted, now 9,087,580, issued on Jul. 21, 2015.
Application 15/292,098 is a continuation of application No. 14/738,349, filed on Jun. 12, 2015, granted, now 9,490,012.
Application 13/244,812 is a continuation of application No. 12/545,623, filed on Aug. 21, 2009, granted, now 8,159,868, issued on Apr. 17, 2012.
Claims priority of provisional application 61/091,071, filed on Aug. 22, 2008.
Prior Publication US 2017/0032842 A1, Feb. 2, 2017
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 14/00 (2006.01); G11C 11/14 (2006.01); G11C 11/404 (2006.01); G11C 11/56 (2006.01); G11C 13/00 (2006.01); H01L 27/108 (2006.01); H01L 27/24 (2006.01); H01L 29/78 (2006.01); H01L 27/102 (2006.01); H01L 45/00 (2006.01); G06F 3/06 (2006.01)
CPC G11C 14/0045 (2013.01) [G06F 3/0619 (2013.01); G06F 3/0647 (2013.01); G06F 3/0685 (2013.01); G11C 11/14 (2013.01); G11C 11/404 (2013.01); G11C 11/5678 (2013.01); G11C 11/5685 (2013.01); G11C 13/0004 (2013.01); G11C 13/0007 (2013.01); G11C 13/0033 (2013.01); H01L 27/108 (2013.01); H01L 27/1023 (2013.01); H01L 27/10802 (2013.01); H01L 27/10897 (2013.01); H01L 27/24 (2013.01); H01L 27/2445 (2013.01); H01L 27/2463 (2013.01); H01L 29/7841 (2013.01); H01L 45/06 (2013.01); H01L 45/065 (2013.01); H01L 45/085 (2013.01); H01L 45/1233 (2013.01); H01L 45/1253 (2013.01); H01L 45/141 (2013.01); H01L 45/146 (2013.01); H01L 45/147 (2013.01); G11C 2013/0045 (2013.01); G11C 2013/0078 (2013.01); G11C 2211/4016 (2013.01); G11C 2211/5643 (2013.01); G11C 2213/31 (2013.01); G11C 2213/32 (2013.01)] 21 Claims
OG exemplary drawing
 
1. A semiconductor memory cell comprising:
a silicon controlled rectifier device comprising a floating body having a first conductivity type selected from n-type conductivity type and p-type conductivity type and configured to store data when power is applied to said cell;
a nonvolatile memory comprising a resistance change element configured to store data stored in said silicon controlled rectifier device upon transfer thereto;
a buried layer region having a second conductivity type selected from said n-type conductivity type and said p-type conductivity type and being different from said first conductivity type.