	US 9,812,200 B2
	Concurrent read and write operations in a serial flash device
Gideon Intrater, Sunnyvale, CA (US); Bard Pedersen, Fremont, CA (US); Shane Hollmer, Grass Valley, CA (US); Derric Lewis, Sunnyvale, CA (US); and Stephen Trinh, San Jose, CA (US)
Assigned to Adesto Technologies Corporation, Santa Clara, CA (US)
Filed by Adesto Technologies Corporation, Sunnyvale, CA (US)
Filed on May 22, 2015, as Appl. No. 14/719,814.
Claims priority of provisional application 62/021,840, filed on Jul. 8, 2014.
Prior Publication US 2016/0012891 A1, Jan. 14, 2016
Int. Cl. G11C 13/00 (2006.01); G06F 13/16 (2006.01); G11C 16/32 (2006.01); G11C 29/02 (2006.01); G11C 7/22 (2006.01)

CPC G11C 13/0069 (2013.01) [G06F 13/1668 (2013.01); G11C 13/004 (2013.01); G11C 13/0011 (2013.01); G11C 13/0023 (2013.01); G11C 13/0061 (2013.01); G11C 7/227 (2013.01); G11C 16/32 (2013.01); G11C 29/021 (2013.01); G11C 29/028 (2013.01); G11C 2213/71 (2013.01); G11C 2216/20 (2013.01)]

20 Claims

1. A non-volatile memory (NVM) device, comprising:

a) an interface configured to receive write and read commands from a host;

b) a memory array comprising a plurality of NVM cells arranged in a plurality of array planes;

c) a memory controller configured to execute a write operation on a first of the plurality of array planes in response to a write command, and to execute a read operation on a second of the plurality of array planes in response to a read command, wherein the memory controller is configured to suspend the write operation in response to detection of the read command during execution of the write operation, and wherein the memory controller is configured to resume the write operation during execution of the read operation on the memory array; and

d) a regulator circuit configured to supply a bias voltage for the write operation, wherein the read command comprises a time slot to allow capture of a state of the write operation, and to transition the regulator circuit to a standby state, in order to suspend the write operation.