US 9,812,199 B2
Electronic device with semiconductor memory having variable resistance elements for storing data and associated driving circuitry
Dong-Keun Kim, Icheon-Si (KR)
Assigned to SK hynix Inc., Icheon-Si (KR)
Filed by SK hynix Inc., Icheon-Si (KR)
Filed on Sep. 30, 2014, as Appl. No. 14/503,100.
Claims priority of application No. 10-2014-0050034 (KR), filed on Apr. 25, 2014.
Prior Publication US 2015/0310914 A1, Oct. 29, 2015
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 13/00 (2006.01); G11C 11/16 (2006.01)
CPC G11C 13/0069 (2013.01) [G11C 11/161 (2013.01); G11C 11/1659 (2013.01)] 18 Claims
OG exemplary drawing
 
1. An electronic device including a semiconductor memory unit, the semiconductor memory unit comprising:
a plurality of columns; and
a data line and a data line,
each of the plurality of columns including:
a bit line and a bit line bar;
a source line;
a plurality of storage cells connected between the bit line and the bit line bar
a first sourcing element connected between the bit line and a first node, and configured to be turned on in a read operation;
a second sourcing element connected between the bit line bar and a second node, and configured to be turned on in the read operation;
a first write element connected between the bit line and the first node, and configured to be turned on in a write operation;
a second write element connected between the bit line bar and the second node, and configured to be turned on in the write operation;
a first PMOS transistor having one end connected to the first node and the other end applied with a power supply voltage, and configured to be turned on and off in response to a voltage of the second node;
a second PMOS transistor having one end connected to the second node and the other end applied with the power supply voltage, and configured to be turned on and off in response to a voltage of the first node;
a first NMOS transistor having one end connected to the first node and the other end applied with a ground voltage, and configured to be turned on and off in response to a voltage of the second node;
a second NMOS transistor having one end connected to the second node and the other end applied with the ground voltage, and configured to be turned on and off in response to a voltage of the first node;
a sinking element configured to apply the ground voltage to the source line in the read operation;
a first column selection element connected between the first node and the data line, and configured to be turned on when a corresponding column is selected; and
a second column selection element connected between the second node and the data line bar, and configured to be turned on when the corresponding column is selected,
wherein each of the plurality of storage cells includes:
a first variable resistance element connected between the bit line and the source line; and
a second variable resistance element connected between the bit line bar and the source line.