US 9,812,196 B2
Geometry dependent voltage biases for asymmetric resistive memories
Frederick Perner, Palo Alto, CA (US)
Assigned to Hewlett Packard Enterprise Development LP, Houston, TX (US)
Appl. No. 15/30,092
Filed by Hewlett Packard Enterprise Development LP, Houston, TX (US)
PCT Filed Oct. 28, 2013, PCT No. PCT/US2013/067071
§ 371(c)(1), (2) Date Apr. 18, 2016,
PCT Pub. No. WO2015/065316, PCT Pub. Date May 7, 2015.
Prior Publication US 2016/0247563 A1, Aug. 25, 2016
Int. Cl. G11C 13/00 (2006.01); G11C 5/02 (2006.01); G11C 5/14 (2006.01)
CPC G11C 13/004 (2013.01) [G11C 5/025 (2013.01); G11C 5/147 (2013.01); G11C 13/0023 (2013.01); G11C 13/0069 (2013.01); G11C 13/0007 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system comprising:
a multi-plane memory array with shared crossbars and memory elements accessed through the shared crossbars;
support circuitry comprising a bias multiplexer to determine an orientation of a target memory element in the multi-plane memory array and output voltage biases with a polarity based on the orientation of the target memory element.