US 9,812,195 B2
Nonvolatile semiconductor memory device
Hiroyuki Nagashima, Yokohama (JP); and Hirofumi Inoue, Kamakura (JP)
Assigned to TOSHIBA MEMORY CORPORATION, Minato-ku (JP)
Filed by TOSHIBA MEMORY CORPORATION, Minato-ku (JP)
Filed on Dec. 23, 2016, as Appl. No. 15/389,609.
Application 15/389,609 is a continuation of application No. 15/080,930, filed on Mar. 25, 2016, granted, now 9,543,011.
Application 15/080,930 is a continuation of application No. 14/589,554, filed on Jan. 5, 2015, granted, now 9,299,426.
Application 14/589,554 is a continuation of application No. 13/058,952, granted, now 8,964,447, previously published as PCT/JP2009/062019, filed on Jun. 24, 2009.
Claims priority of application No. 2008-208426 (JP), filed on Aug. 13, 2008.
Prior Publication US 2017/0103807 A1, Apr. 13, 2017
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 11/00 (2006.01); G11C 13/00 (2006.01)
CPC G11C 13/003 (2013.01) 16 Claims
OG exemplary drawing
 
1. A nonvolatile semiconductor memory device, comprising:
a cell array including a plurality of unit cell arrays arranged in a matrix, one of the unit cell arrays including a plurality of bit lines, a plurality of word lines intersecting the bit lines, and a plurality of electrically rewritable memory cells connected at intersections of the bit lines and the word lines between both lines and each including a variable resistance element; and
a control circuit corresponding to one of the unit cell arrays configured to control voltages applied to the bit lines and the word lines, the control circuit including a row control circuit to select the word lines, and a column control circuit to select the bit lines, at least a part of the control circuit being provided beneath the corresponding unit cell array,
the control circuit, during data write to the cell array, simultaneously writing a part of data having a plurality of bits to at least one of the memory cells belonging to one of the unit cell arrays, and another part of the data to at least one of the memory cells belonging another of the unit cell arrays, the memory cells written simultaneously being physically separated apart more than one memory cell from each other.