US 9,812,194 B1
Decoding method, memory storage device and memory control circuit unit
Wei Lin, Taipei (TW); Yu-Cheng Hsu, Yilan County (TW); and Szu-Wei Chen, New Taipei (TW)
Assigned to PHISON ELECTRONICS CORP., Miaoli (TW)
Filed by PHISON ELECTRONICS CORP., Miaoli (TW)
Filed on Apr. 7, 2017, as Appl. No. 15/481,473.
Claims priority of application No. 106103993 A (TW), filed on Feb. 7, 2017.
Int. Cl. G11C 16/04 (2006.01); G11C 11/56 (2006.01); G11C 16/08 (2006.01)
CPC G11C 11/5642 (2013.01) [G11C 11/5628 (2013.01); G11C 16/0466 (2013.01); G11C 16/08 (2013.01)] 30 Claims
OG exemplary drawing
 
1. A decoding method, for a rewritable non-volatile memory module comprising a plurality of memory cells, the decoding method comprising:
obtaining usage state information of a plurality of first memory cells among the memory cells;
reading a plurality of second memory cells among the memory cells by using a first read voltage level to obtain at least one first bit and reading the second memory cells by using a second read voltage level to obtain at least one second bit according to the usage state information, wherein the at least one first bit corresponds to a storage state of a first part of memory cells among the second memory cells, the at least one second bit corresponds to a storage state of a second part of memory cells among the second memory cells, and the first read voltage level is different from the second read voltage level; and
decoding a plurality of third bits comprising the at least one first bit and the at least one second bit.