|1. A superconducting gate memory circuit comprising:
a Josephson D-gate circuit configured to set a digital state as one of a first data state and a second data state in response
to a write enable single flux quantum (SFQ) pulse provided on a write enable input and a respective presence of or absence
of a write data SFQ pulse provided on a data write input; and
a storage loop coupled to the Josephson D-gate, the storage loop being configured to store the digital state and to readout
the digital state at an output in response to a read enable SFQ pulse provided on a read enable input and a read data SFQ
pulse provided on a read data input.