US 9,812,192 B1
Superconducting gate memory circuit
Randall M. Burnett, Catonsville, MD (US); and Quentin P. Herr, Ellicott City, MD (US)
Assigned to Northrop Grumman Systems Corporation, Falls Church, VA (US)
Filed by Randall M. Burnett, Catonsville, MD (US); and Quentin P. Herr, Ellicott City, MD (US)
Filed on Nov. 14, 2016, as Appl. No. 15/351,065.
Claims priority of provisional application 62/383,204, filed on Sep. 2, 2016.
Int. Cl. G11C 11/44 (2006.01)
CPC G11C 11/44 (2013.01) 20 Claims
OG exemplary drawing
 
1. A superconducting gate memory circuit comprising:
a Josephson D-gate circuit configured to set a digital state as one of a first data state and a second data state in response to a write enable single flux quantum (SFQ) pulse provided on a write enable input and a respective presence of or absence of a write data SFQ pulse provided on a data write input; and
a storage loop coupled to the Josephson D-gate, the storage loop being configured to store the digital state and to readout the digital state at an output in response to a read enable SFQ pulse provided on a read enable input and a read data SFQ pulse provided on a read data input.