US 9,812,191 B1
Memory circuit with negative voltage assist
Avinash Chander, Jhubei (TW); and Yen-Huei Chen, Jhudong Township (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu (TW)
Filed on Sep. 29, 2016, as Appl. No. 15/279,944.
Int. Cl. G11C 11/419 (2006.01); G11C 11/418 (2006.01)
CPC G11C 11/419 (2013.01) [G11C 11/418 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory device, comprising:
a memory array comprising a first plurality of bit cells arranged along a first column; and
a negative bit line (NBL) circuit, coupled to the memory array, and comprising:
a first pair of conducting gates that are coupled to the first plurality of bit cells through a bit line (BL) and a bit bar line (BBL) of the first column, respectively; and
a pair of trigger circuits, coupled to the first pair of conducting gates, respectively, and configured to monitor voltage levels present on the BL and BBL of the first column through the respective first pair of conducting gates, and based on the monitored voltage levels, to assert an NBL enable signal so as to cause a negative voltage to be applied on either the BL or the BBL of the first column.