US 9,812,190 B2
Cell structure of 4T random access memory, random access memory and operation methods
Liyang Pan, Beijing (CN); Xinhong Hong, Beijing (CN); and Dong Wu, Beijing (CN)
Assigned to TSINGHUA UNIVERSITY, Beijing (CN); and GRADUATE SCHOOL AT SHENZHEN, TSINGHUA UNIVERSITY, Shenzhen, Guangdong (CN)
Appl. No. 14/772,371
Filed by Tsinghua University, Beijing (CN); and Graduate School at Shenzhen, Tsinghua University, Shenzhen, Guangdong (CN)
PCT Filed Apr. 17, 2015, PCT No. PCT/CN2015/076891
§ 371(c)(1), (2) Date Sep. 2, 2015,
PCT Pub. No. WO2015/158305, PCT Pub. Date Oct. 22, 2015.
Claims priority of application No. 2014 1 0155104 (CN), filed on Apr. 17, 2014; and application No. 2014 1 0729870 (CN), filed on Dec. 4, 2014.
Prior Publication US 2016/0111146 A1, Apr. 21, 2016
Int. Cl. G11C 11/419 (2006.01); G11C 11/406 (2006.01); G11C 11/412 (2006.01); G11C 11/418 (2006.01); G11C 11/403 (2006.01)
CPC G11C 11/419 (2013.01) [G11C 11/406 (2013.01); G11C 11/412 (2013.01); G11C 11/418 (2013.01); G11C 11/403 (2013.01); G11C 11/4125 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A cell structure of a random access memory, comprising: a first N-type transistor (N1), a first P-type transistor (P1), a second N-type transistor (NG1) and a second P-type transistor (PG1); wherein
a source electrode of the first N-type transistor (N1) is connected to an adjustable low voltage (VSSI), a source electrode of the first P-type transistor (P1) is connected to an adjustable high voltage (VDDI), a drain electrode of the first N-type transistor (N1) is connected to a gate electrode of the first P-type transistor (P1), a gate electrode of the first N-type transistor (N1) is connected to a drain electrode of the first P-type transistor (P1),
a drain electrode of the second N-type transistor (NG1) is connected to a bit line (BL), a gate electrode of the second N-type transistor (NG1) is connected to a write word line (WWL), a source electrode of the second N-type transistor (NG1) is connected to a first node (Q) between the gate electrode of the first N-type transistor (N1) and the drain electrode of the first P-type transistor (P1),
a drain electrode of the second P-type transistor (PG1) is connected to a complementary bit line (BLn), a gate electrode of the second P-type transistor (PG1) is connected to a read word line (RWL), a source electrode of the second P-type transistor (PG1) is connected to a second node (Qn) between the drain electrode of the first N-type transistor (N1) and the gate electrode of the first P-type transistor (P1).