US 9,812,189 B2
Read and write apparatus and method for a dual port memory
Pramod Kolar, Hillsboro, OR (US); Wei-Hsiang Ma, Portland, OR (US); and Gunjan H. Pandya, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jun. 4, 2015, as Appl. No. 14/731,319.
Prior Publication US 2016/0358643 A1, Dec. 8, 2016
Int. Cl. G11C 11/00 (2006.01); G11C 11/419 (2006.01); G11C 8/14 (2006.01); G11C 8/16 (2006.01); G11C 11/418 (2006.01)
CPC G11C 11/419 (2013.01) [G11C 8/14 (2013.01); G11C 8/16 (2013.01); G11C 11/418 (2013.01)] 19 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a memory array;
a first logic to detect whether first and second word-lines for a row of the memory array are active; and
a second logic to deactivate one of the first and second wordlines such that one of the first and second wordlines is active for the row,
wherein the memory array includes memory bit-cells, at least one of which is accessible via at least first and second ports, wherein the first port is associated with the first wordline and the second port is associated with the second wordline, and wherein the apparatus further comprises:
a first switch coupled to first and second bit-lines associated with a memory bit-cell, wherein the first and second bit-lines are non-complementary bit-lines, wherein the first switch is operable to re-route data on the first and second bit-lines to the first and second ports, respectively,
wherein the first logic is to detect whether the first and second wordlines are addressing a same row of the memory array,
wherein the second logic is to determine whether the first and second wordlines have signals on them which overlap each other for at least a duration of time, and
wherein the signal on the first or second wordlines which arrives later is suppressed while a pulse width of the signal on the first or second wordlines that arrives early is extended.