US 9,812,188 B2
Static random-access memory (SRAM) sensor for bias temperature instability
Niladri Narayan Mojumder, San Diego, CA (US); Zhongze Wang, San Diego, CA (US); Xiaonan Chen, San Diego, CA (US); Stanley Seungchul Song, San Diego, CA (US); and Choh Fei Yeap, San Diego, CA (US)
Assigned to QUALCOMM Incorporated, San Diego, CA (US)
Filed by QUALCOMM Incorporated, San Diego, CA (US)
Filed on Feb. 25, 2015, as Appl. No. 14/631,603.
Prior Publication US 2016/0247554 A1, Aug. 25, 2016
Int. Cl. G11C 11/00 (2006.01); G11C 11/419 (2006.01); G11C 7/20 (2006.01); G11C 11/417 (2006.01); G11C 29/02 (2006.01); G11C 29/24 (2006.01); G11C 29/50 (2006.01); G11C 29/04 (2006.01)
CPC G11C 11/419 (2013.01) [G11C 7/20 (2013.01); G11C 11/417 (2013.01); G11C 29/021 (2013.01); G11C 29/028 (2013.01); G11C 29/24 (2013.01); G11C 29/50 (2013.01); G11C 29/50004 (2013.01); G11C 2029/0407 (2013.01); G11C 2029/0409 (2013.01); G11C 2029/5002 (2013.01)] 30 Claims
OG exemplary drawing
 
1. An apparatus comprising:
an array of static random-access memory (SRAM) cells, wherein each SRAM cell of the array has a size within a target range, wherein each SRAM cell of the array of SRAM cells is configured to be initialized to a corresponding initial state based on a supply voltage received during a power-up operation of the array; and
circuitry configured to initiate a corrective action related to the array, the corrective action based on a number of the SRAM cells of the array of SRAM cells that, responsive to the power-up operation, have a particular initial state.